Editing Intel MCS-51 (section)

== Instruction set ==
Instructions are all 1 to 3 bytes long, consisting of an initial opcode byte, followed by up to 2 bytes of operands.

{{frac|1|4}} of the opcode bytes, '''''x''0–''x''3''', are used for irregular opcodes.

{{frac|3|4}} of the opcode bytes, '''''x''4–''x''F''', are assigned to 16 basic ALU instructions with 12 possible operands.  The least significant [[nibble]] of the opcode selects the primary operand as follows:

* '''''x''8–''x''F''': Register direct, R0–R7.
* '''''x''6–''x''7''': Register indirect, @R0 or @R1.
* '''''x''5''': Memory direct, a following byte specifies an IRAM or SFR location.
* '''''x''4''': Immediate, a following byte specifies an 8-bit constant.  When the operand is a destination ({{code|lang=asm|INC operand}}, {{code|lang=asm|DEC operand}}) ''or'' the operation already includes an immediate source ({{code|lang=asm|MOV operand,#data}}, {{code|lang=asm|CJNE operand,#data,offset}}), this instead specifies that the accumulator is used.

The most significant nibble specifies the operation as follows.  Not all support all addressing modes; the immediate mode in particular is unavailable when the primary operand is written to.  Instruction mnemonics use ''destination'', ''source'' operand order.

; 0''y''{{colon}} {{code|lang=asm|INC operand}}: Increment the specified operand.  Immediate mode (opcode 0x04) specifies the accumulator, {{code|lang=asm|INC A}}.
; 1''y''{{colon}} {{code|lang=asm|DEC operand}}: Decrement the specified operand.  Immediate mode (opcode 0x14) specifies the accumulator, {{code|lang=asm|DEC A}}.
; 2''y''{{colon}} {{code|lang=asm|ADD A,operand}}: Add the operand to the accumulator, A.  Opcode 0x23 ({{code|lang=asm|RL A}}, "rotate left" but actually a [[shift left]]) may be thought of as {{code|lang=asm|ADD A,A}}.
; 3''y''{{colon}} {{code|lang=asm|ADDC A,operand}}: Add the operand, plus the C bit, to the accumulator.  Opcode 0x33 ({{code|lang=asm|RLC A}}, rotate left through carry) may be thought of as {{code|lang=asm|ADDC A,A}}.
; 4''y''{{colon}} {{code|lang=asm|ORL A,operand}}: Logical OR the operand into the accumulator.  Two memory-destination forms of this operation, {{code|lang=asm|ORL address,#data}} and {{code|lang=asm|ORL address,A}}, are specified by opcodes 0x43 and 0x42.
; 5''y''{{colon}} {{code|lang=asm|ANL A,operand}}: Logical AND the operand into the accumulator.  Two memory-destination forms of this operation, {{code|lang=asm|ANL address,#data}} and {{code|lang=asm|ANL address,A}}, are specified by opcodes 0x53 and 0x52.
; 6''y''{{colon}} {{code|lang=asm|XRL A,operand}}: Logical exclusive-OR the operand into the accumulator.  Two memory-destination forms of this operation, {{code|lang=asm|XRL address,#data}} and {{code|lang=asm|XRL address,A}}, are specified by opcodes 0x63 and 0x62.
; 7''y''{{colon}} {{code|lang=asm|MOV operand,#data}}: Move immediate to the operand.  Immediate mode (opcode 0x74) specifies the accumulator, {{code|lang=asm|MOV A,#data}}.
; 8''y''{{colon}} {{code|lang=asm|MOV address,operand}}: Move value to an IRAM or SFR register.  Immediate mode (opcode 0x84) is not used for this operation, as it duplicates opcode 0x75.
; 9''y''{{colon}} {{code|lang=asm|SUBB A,operand}}: Subtract the operand from the accumulator.  This operation borrows and there is no subtract ''without'' borrow.
; A''y''{{colon}} {{code|lang=asm|MOV operand,address}}: Move value from an IRAM or SFR register.  Immediate mode (opcode 0xA4) is not used, as immediates serve only as sources. Memory direct mode (opcode 0xA5) is not used, as it duplicates 0x85. 
; B''y''{{colon}} {{code|lang=asm|CJNE operand,#data,offset}}: Compare ''operand'' to the immediate {{code|lang=asm|#data}}, and jump to {{nowrap|PC + ''offset''}} if not equal.  Immediate and memory direct modes (opcodes 0xB4 and 0xB5) compare the operand against the accumulator, {{code|lang=asm|CJNE A,operand,offset}}.  Note that there is no compare and jump if equal instruction, {{code|lang=asm|CJE}}.
; C''y''{{colon}} {{code|lang=asm|XCH A,operand}}: Exchange the accumulator and the operand.  Immediate mode (opcode 0xC4) is not used for this operation.
; D''y''{{colon}} {{code|lang=asm|DJNZ operand,offset}}: Decrement the operand, and jump to {{nowrap|PC + ''offset''}} if the result is non-zero.  Immediate mode (opcode 0xD4), and register indirect mode (0xD6, 0xD7) are not used.
; E''y''{{colon}} {{code|lang=asm|MOV A,operand}}: Move operand to the accumulator.  Immediate mode is not used for this operation (opcode 0xE4), as it duplicates opcode 0x74.
; F''y''{{colon}} {{code|lang=asm|MOV operand,A}}: Move accumulator to the operand.  Immediate mode (opcode 0xF4) is not used, as it would have no effect.

Only the {{code|lang=asm|ADD}}, {{code|lang=asm|ADDC}}, and {{code|lang=asm|SUBB}} instructions set PSW flags.  The {{code|lang=asm|INC}}, {{code|lang=asm|DEC}}, and logical instructions do not.  The {{code|lang=asm|CJNE}} instruction modifies the C bit only, to the borrow that results from {{nowrap|''operand1'' − ''operand2''}}.

The irregular instructions comprise 64 opcodes, having more limited addressing modes, plus several opcodes scavenged from inapplicable modes in the regular instructions.

{| class=wikitable
|+ 8051/8052 irregular instructions
|-
! Opcode !! ''x''0 !! ''x''1 !! ''x''2 !! ''x''3 !! ''x''4
|-
! 0''y''
| {{code|lang=asm|NOP}}
| rowspan=16 | {{ubl
 | {{code|lang=asm|AJMP addr11}},
 | {{nobr|{{code|lang=asm|ACALL addr11}}}}
 }}
| {{code|lang=asm|LJMP addr16}} || {{code|lang=asm|RR A}} (rotate right) || {{n/a|{{code|lang=asm|INC A}}}}
|-
! 1''y''
| {{code|lang=asm|JBC bit,offset}} (jump if bit set with clear)
| {{nobr|{{code|lang=asm|LCALL addr16}}}} || {{code|lang=asm|RRC A}} (rotate right through carry) || {{n/a|{{code|lang=asm|DEC A}}}}
|-
! 2''y''
| {{code|lang=asm|JB bit,offset}} (jump if bit set)
| {{code|lang=asm|RET}} || {{code|lang=asm|RL A}} (rotate left) || {{n/a|{{code|lang=asm|ADD A,#data}}}}
|-
! 3''y''
| {{code|lang=asm|JNB bit,offset}} (jump if bit clear)
| {{code|lang=asm|RETI}} || {{code|lang=asm|RLC A}} (rotate left through carry) || {{n/a|{{code|lang=asm|ADDC A,#data}}}}
|-
! 4''y''
| {{code|lang=asm|JC offset}} (jump if carry set)
| {{n/a|{{code|lang=asm|ORL address,A}}}} || {{n/a|{{code|lang=asm|ORL address,#data}}}} || {{n/a|{{code|lang=asm|ORL A,#data}}}}
|-
! 5''y''
| {{code|lang=asm|JNC offset}} (jump if carry clear)
| {{n/a|{{code|lang=asm|ANL address,A}}}} || {{n/a|{{code|lang=asm|ANL address,#data}}}} || {{n/a|{{code|lang=asm|ANL A,#data}}}}
|-
! 6''y''
| {{code|lang=asm|JZ offset}} (jump if zero)
| {{n/a|{{code|lang=asm|XRL address,A}}}} || {{n/a|{{code|lang=asm|XRL address,#data}}}} || {{n/a|{{code|lang=asm|XRL A,#data}}}}
|-
! 7''y''
| {{code|lang=asm|JNZ offset}} (jump if non-zero)
| {{code|lang=asm|ORL C,bit}} || {{code|lang=asm|JMP @A+DPTR}} || {{n/a|{{code|lang=asm|MOV A,#data}}}}
|-
! 8''y''
| {{code|lang=asm|SJMP offset}} (short jump)
| {{code|lang=asm|ANL C,bit}} || {{code|lang=asm|MOVC A,@A+PC}} || {{code|lang=asm|DIV AB}}
|-
! 9''y''
| {{code|lang=asm|MOV DPTR,#data16}}
| {{code|lang=asm|MOV bit,C}} || {{code|lang=asm|MOVC A,@A+DPTR}} || {{n/a|{{code|lang=asm|SUBB A,#data}}}}
|-
! A''y''
| {{code|lang=asm|ORL C,/bit}}
| {{code|lang=asm|MOV C,bit}} || {{code|lang=asm|INC DPTR}} || {{code|lang=asm|MUL AB}}
|-
! B''y''
| {{code|lang=asm|ANL C,/bit}}
| {{code|lang=asm|CPL bit}} || {{code|lang=asm|CPL C}} || {{n/a|{{code|lang=asm|CJNE A,#data,offset}}}}
|-
! C''y''
| {{code|lang=asm|PUSH address}}
| {{code|lang=asm|CLR bit}} || {{code|lang=asm|CLR C}} || {{code|lang=asm|SWAP A}}
|-
! D''y''
| {{code|lang=asm|POP address}}
| {{code|lang=asm|SETB bit}} || {{code|lang=asm|SETB C}} || {{code|lang=asm|DA A}} (decimal adjust)
|-
! E''y''
| {{code|lang=asm|MOVX A,@DPTR}}
| {{code|lang=asm|MOVX A,@R0}} || {{code|lang=asm|MOVX A,@R1}} || {{code|lang=asm|CLR A}}
|-
! F''y''
| {{code|lang=asm|MOVX @DPTR,A}}
| {{code|lang=asm|MOVX @R0,A}} || {{code|lang=asm|MOVX @R1,A}} || {{code|lang=asm|CPL A}}
|}

; 85: {{code|lang=asm|MOV address,address}} move directly between two IRAM or SFR registers.
; A5: ''Unused'' 
; B5: {{code|lang=asm|CJNE A,address,offset}} compare accumulator to an IRAM or SFR register, and jump to {{nowrap|PC + ''offset''}} if not equal.
; D6–7: {{code|lang=asm|XCHD A,@R0–1}} exchange low-order nibble of operands.

The {{code|lang=asm|SJMP}} (short jump) opcode takes a signed relative offset byte operand and transfers control there relative to the address of the following instruction. The {{code|lang=asm|AJMP}}/{{code|lang=asm|ACALL}} opcodes combine the three most significant bits of the opcode byte with the following byte to specify an 11-bit destination that is used to replace 11 bottom bits of the PC register (top 5 bits of PC register remain intact).  For larger addresses, the {{code|lang=asm|LJMP}} and {{code|lang=asm|LCALL}} instructions allow a 16-bit destination.

One of the reasons for the 8051's popularity is its range of operations on single bits.  Bits are always specified by absolute addresses; there is no register-indirect or indexed addressing.  Instructions that operate on single bits are:

* {{code|lang=asm|SETB bit}}, {{code|lang=asm|CLR bit}}, {{code|lang=asm|CPL bit}}: Set, clear, or complement the specified bit
* {{code|lang=asm|JB bit,offset}}: Jump if bit set
* {{code|lang=asm|JNB bit,offset}}: Jump if bit clear
* {{code|lang=asm|JBC bit,offset}}: Jump if bit set, and clear bit
* {{code|lang=asm|MOV C,bit}}, {{code|lang=asm|MOV bit,C}}: Move the specified bit to the carry bit, or vice versa
* {{code|lang=asm|ORL C,bit}}, {{code|lang=asm|ORL C,/bit}}: Or the bit (or its complement) to the carry bit
* {{code|lang=asm|ANL C,bit}}, {{code|lang=asm|ANL C,/bit}}: And the bit (or its complement) to the carry bit

A bit operand is written in the form {{code|address.number}}. Because the carry flag is bit 7 of the bit-addressable program status word, the {{code|lang=asm|SETB C}}, {{code|lang=asm|CLR C}} and {{code|lang=asm|CPL C}} instructions are shorter equivalents to {{code|lang=asm|SETB PSW.7}}, {{code|lang=asm|CLR PSW.7}} and {{code|lang=asm|CPL PSW.7}}.