Editing Dynamic random-access memory (section)

===Proposed cell designs===
The one-transistor, zero-capacitor (1T, or 1T0C) DRAM cell has been a topic of research since the late-1990s. ''1T DRAM'' is a different way of constructing the basic DRAM memory cell, distinct from the classic one-transistor/one-capacitor (1T/1C) DRAM cell, which is also sometimes referred to as ''1T DRAM'', particularly in comparison to the 3T and 4T DRAM which it replaced in the 1970s.

In 1T DRAM cells, the bit of data is still stored in a capacitive region controlled by a transistor, but this capacitance is no longer provided by a separate capacitor. 1T DRAM is a "capacitorless" bit cell design that stores data using the parasitic body capacitance that is inherent to [[silicon on insulator]] (SOI) transistors. Considered a nuisance in logic design, this [[floating body effect]] can be used for data storage. This gives 1T DRAM cells the greatest density as well as allowing easier integration with high-performance logic circuits since they are constructed with the same SOI process technologies.<ref>{{cite web |url=https://aes2.org/publications/par/num/ |title=Pro Audio Reference |access-date=2024-08-08}}</ref>

Refreshing of cells remains necessary, but unlike with 1T1C DRAM, reads in 1T DRAM are non-destructive; the stored charge causes a detectable shift in the [[threshold voltage]] of the transistor.<ref>{{cite conference|first=Jean-Michel|last=Sallese|title=Principles of the 1T Dynamic Access Memory Concept on SOI|conference=MOS Modeling and Parameter Extraction Group Meeting|location=Wroclaw, Poland|date=2002-06-20|url=http://legwww.epfl.ch/ekv/mos-ak/wroclaw/MOS-AK_JMS.pdf|access-date=2007-10-07|url-status=dead|archive-url=https://web.archive.org/web/20071129114317/http://legwww.epfl.ch/ekv/mos-ak/wroclaw/MOS-AK_JMS.pdf|archive-date=2007-11-29}}</ref> Performance-wise, access times are significantly better than capacitor-based DRAMs, but slightly worse than SRAM. There are several types of 1T DRAMs: the commercialized [[Z-RAM]] from Innovative Silicon, the TTRAM<ref>{{cite book|author1=F. Morishita|title=Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005|display-authors=etal|chapter=A capacitorless twin-transistor random access memory (TTRAM) on SOI|date=21 September 2005|volume=Custom Integrated Circuits Conference 2005|pages=428–431|doi=10.1109/CICC.2005.1568699|isbn=978-0-7803-9023-2|s2cid=14952912}}</ref> from Renesas and the [[A-RAM]] from the [[University of Granada|UGR]]/[[CNRS]] consortium.