Editing Direct memory access (section)

=== DDIO ===
Further performance-oriented enhancements to the DMA mechanism have been introduced in Intel [[Xeon&nbsp;E5]] processors with their '''Data Direct I/O''' ('''DDIO''') feature, allowing the DMA "windows" to reside within [[CPU cache]]s instead of system RAM. As a result, CPU caches are used as the primary source and destination for I/O, allowing [[network interface controller]]s (NICs) to DMA directly to the Last level cache (L3 cache) of local CPUs and avoid costly fetching of the I/O data from system RAM. As a result, DDIO reduces the overall I/O processing latency, allows processing of the I/O to be performed entirely in-cache, prevents the available RAM bandwidth/latency from becoming a performance bottleneck, and may lower the power consumption by allowing RAM to remain longer in low-powered state.<ref>{{cite web
 | url = http://www.intel.com/content/dam/www/public/us/en/documents/faqs/data-direct-i-o-faq.pdf
 | title = Intel Data Direct I/O (Intel DDIO): Frequently Asked Questions
 | date = March 2012 | access-date = 2015-10-11
 | publisher = [[Intel]] }}</ref><ref>{{cite web
 | url = http://rhelblog.redhat.com/2015/09/29/pushing-the-limits-of-kernel-networking/
 | title = Pushing the Limits of Kernel Networking
 | date = 2015-09-29 | access-date = 2015-10-11
 | author = Rashid Khan | website = redhat.com
}}</ref><ref>{{cite web
 | url = http://www.solarflare.com/content/userfiles/documents/intel_solarflare_webinar_paper.pdf
 | title = Achieving Lowest Latencies at Highest Message Rates with Intel Xeon Processor E5-2600 and Solarflare SFN6122F 10&nbsp;GbE Server Adapter
 | date = 2012-06-07 | access-date = 2015-10-11
 | website = solarflare.com }}</ref><ref>{{cite web
 | url = https://events.static.linuxfound.org/sites/events/files/slides/pushing-kernel-networking.pdf
 | title = Pushing the Limits of Kernel Networking
 | date = 2015-08-19 | access-date = 2015-10-11
 | author = Alexander Duyck | website = linuxfoundation.org
 | page = 5
}}</ref>