Editing Digital electronics (section)

===Design for testability===
There are several reasons for testing a logic circuit. When the circuit is first developed, it is necessary to verify that the design circuit meets the required functional, and timing specifications. When multiple copies of a correctly designed circuit are being manufactured, it is essential to test each copy to ensure that the manufacturing process has not introduced any flaws.<ref>Brown S & Vranesic Z. (2009). Fundamentals of Digital Logic with VHDL Design. 3rd ed. New York, N.Y.: Mc Graw Hill.</ref>

A large logic machine (say, with more than a hundred logical variables) can have an astronomical number of possible states. Obviously, factory testing every state of such a machine is unfeasible, for even if testing each state only took a microsecond, there are more possible states than there are microseconds since the universe began!

Large logic machines are almost always designed as assemblies of smaller logic machines. To save time, the smaller sub-machines are isolated by permanently installed ''design for test'' circuitry and are tested independently. One common testing scheme provides a test mode that forces some part of the logic machine to enter a ''test cycle''. The test cycle usually exercises large independent parts of the machine.

[[Boundary scan]] is a common test scheme that uses [[serial communication]] with external test equipment through one or more [[shift register]]s known as ''scan chains''. Serial scans have only one or two wires to carry the data, and minimize the physical size and expense of the infrequently used test logic. After all the test data bits are in place, the design is reconfigured to be in ''normal mode'' and one or more clock pulses are applied, to test for faults (e.g. stuck-at low or stuck-at high) and capture the test result into flip-flops or latches in the scan shift register(s). Finally, the result of the test is shifted out to the block boundary and compared against the predicted ''good machine'' result.

In a board-test environment, serial-to-parallel testing has been formalized as the [[JTAG]] standard.