Editing Central processing unit (section)

===Address generation unit===
{{Main|Address generation unit}}
The address generation unit (AGU), sometimes also called the address computation unit (ACU),<ref>{{cite web |last1=Van Berkel |first1=Cornelis |last2=Meuwissen |first2=Patrick |date=January 12, 2006 |title=Address generation unit for a processor (US 2006010255 A1 patent application) |url=https://patents.google.com/patent/US20060010255 |url-status=live |archive-url=https://web.archive.org/web/20160418074853/http://www.google.com/patents/US20060010255 |archive-date=April 18, 2016 |access-date=December 8, 2014 |website=google.com}} {{verify source|date=August 2019|reason=This ref was deleted ([[Special:Diff/897932214]]) by a bug in VisualEditor and later restored by a bot from the original cite at [[Special:Permalink/897793086]] cite #1 - please verify the cite's accuracy and remove this {verify source} template. [[User:GreenC bot/Job 18]]}}</ref> is an [[execution unit]] inside the CPU that calculates [[Memory address|addresses]] used by the CPU to access [[main memory]]. By having address calculations handled by separate circuitry that operates in parallel with the rest of the CPU, the number of [[CPU cycle]]s required for executing various [[machine instruction]]s can be reduced, bringing performance improvements.

While performing various operations, CPUs need to calculate memory addresses required for fetching data from the memory; for example, in-memory positions of [[array element]]s must be calculated before the CPU can fetch the data from actual memory locations. Those address-generation calculations involve different [[integer arithmetic operation]]s, such as addition, subtraction, [[modulo operation]]s, or [[bit shift]]s. Often, calculating a memory address involves more than one general-purpose machine instruction, which do not necessarily [[Instruction cycle|decode and execute]] quickly. By incorporating an AGU into a CPU design, together with introducing specialized instructions that use the AGU, various address-generation calculations can be offloaded from the rest of the CPU, and can often be executed quickly in a single CPU cycle.

Capabilities of an AGU depend on a particular CPU and its [[Computer architecture|architecture]]. Thus, some AGUs implement and expose more address-calculation operations, while some also include more advanced specialized instructions that can operate on multiple [[operand]]s at a time. Some CPU architectures include multiple AGUs so more than one address-calculation operation can be executed simultaneously, which brings further performance improvements due to the [[superscalar]] nature of advanced CPU designs. For example, [[Intel]] incorporates multiple AGUs into its [[Sandy Bridge (microarchitecture)|Sandy Bridge]] and [[Haswell (microarchitecture)|Haswell]] [[microarchitecture]]s, which increase bandwidth of the CPU memory subsystem by allowing multiple memory-access instructions to be executed in parallel.