Editing X86 (section)

===32-bit===
[[File:Table of x86 Registers svg.svg|thumb|upright=2.2|Registers available in the x86-64 instruction set]]

With the advent of the 32-bit [[Intel 80386|80386]] processor, the 16-bit general-purpose registers, base registers, index registers, instruction pointer, and [[FLAGS register]], but not the segment registers, were expanded to 32&nbsp;bits. The nomenclature represented this by prefixing an "'''E'''" (for "extended") to the register names in [[x86 assembly language]]. Thus, the AX register corresponds to the lower 16&nbsp;bits of the new 32-bit EAX register, SI corresponds to the lower 16&nbsp;bits of ESI, and so on. The general-purpose registers, base registers, and index registers can all be used as the base in addressing modes, and all of those registers except for the stack pointer can be used as the index in addressing modes.

Two new segment registers (FS and GS) were added. With a greater number of registers, instructions and operands, the [[machine code]] format was expanded. To provide backward compatibility, segments with executable code can be marked as containing either 16-bit or 32-bit instructions. Special prefixes allow inclusion of 32-bit instructions in a 16-bit segment or vice versa.

The 80386 had an optional floating-point coprocessor, the [[80387]]; it had eight 80-bit wide registers: st(0) to st(7),<ref>{{cite book|url= http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-1-manual.pdf|title= Intel 64 and IA-32 Architectures Software Developer's Manual Volume 1: Basic Architecture|at= Chapter 8|publisher= Intel|date= March 2013|access-date= April 23, 2013|archive-date= April 2, 2013|archive-url= https://web.archive.org/web/20130402233513/http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-1-manual.pdf|url-status= live}}</ref> like the 8087 and 80287. The 80386 could also use an 80287 coprocessor.<ref>{{cite web|url=http://www.cpu-world.com/CPUs/80287/|title=Intel 80287 family|website=CPU-world|access-date=July 21, 2016|archive-date=August 9, 2016|archive-url=https://web.archive.org/web/20160809185320/http://www.cpu-world.com/CPUs/80287/|url-status=live}}</ref> With the [[80486]] and all subsequent x86 models, the floating-point processing unit (FPU) is integrated on-chip.

The [[Pentium MMX]] added eight 64-bit [[MMX (instruction set)|MMX]] integer vector registers (MM0 to MM7, which share lower bits with the 80-bit-wide FPU stack).<ref>{{cite book|url= http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-1-manual.pdf|title= Intel 64 and IA-32 Architectures Software Developer's Manual Volume 1: Basic Architecture|at= Chapter 9|publisher= Intel|date= March 2013|access-date= April 23, 2013|archive-date= April 2, 2013|archive-url= https://web.archive.org/web/20130402233513/http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-1-manual.pdf|url-status= live}}</ref> With the [[Pentium III]], Intel added a 32-bit [[Streaming SIMD Extensions]] (SSE) control/status register (MXCSR) and eight 128-bit SSE floating-point registers (XMM0 to XMM7).<ref>{{cite book
|url= http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-1-manual.pdf
|title= Intel 64 and IA-32 Architectures Software Developer's Manual Volume 1: Basic Architecture
|at= Chapter 10
|publisher= Intel
|date= March 2013
|access-date= April 23, 2013
|archive-date= April 2, 2013
|archive-url= https://web.archive.org/web/20130402233513/http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-1-manual.pdf
|url-status= live
}}</ref>