Editing Semiconductor device fabrication (section)

====Metal layers====
Once the various semiconductor devices have been [[Integrated circuit#circuitLayers|created]], they must be interconnected to form the desired electrical circuits. This occurs in a series of wafer processing steps collectively referred to as BEOL (not to be confused with ''back end'' of chip fabrication, which refers to the packaging and testing stages). BEOL processing involves creating metal interconnecting wires that are isolated by dielectric layers. The insulating material has traditionally been a form of SiO<sub>2</sub> or a [[silicate glass]], but recently new [[low-κ dielectric|low dielectric constant]] materials, also called low-κ dielectrics, are being used (such as silicon oxycarbide), typically providing dielectric constants around 2.7 (compared to 3.82 for SiO<sub>2</sub>), although materials with constants as low as 2.2 are being offered to chipmakers. 

BEoL has been used since 1995 at the 350nm and 250nm nodes (0.35 and 0.25 micron nodes), at the same time chemical mechanical polishing began to be employed. At the time, 2 metal layers for interconnect, also called metallization<ref>{{cite book | url=https://books.google.com/books?id=nC7wCAAAQBAJ&dq=integrated+circuit+metallization&pg=PA276 | title=Technology of Integrated Circuits | isbn=978-3-662-04160-4 | last1=Widmann | first1=D. | last2=Mader | first2=H. | last3=Friedrich | first3=H. | date=9 March 2013 | publisher=Springer }}</ref> was state-of-the-art.<ref>{{cite web | url=https://www.chiphistory.org/35-beol-origins-the-chip-history-center | title=BEOL Wiring Process for CMOS Logic }}</ref>

Since the 22nm node, some manufacturers have added a new process called middle-of-line (MOL) which connects the transistors to the rest of the interconnect made in the BEoL process. The MOL is often based on tungsten and has upper and lower layers: the lower layer connects the junctions of the transistors, and an upper layer which is a tungsten plug that connects the transistors to the interconnect. Intel at the 10nm node introduced contact-over-active-gate (COAG) which, instead of placing the contact for connecting the transistor close to the gate of the transistor, places it directly over the gate of the transistor to improve transistor density.<ref name="auto7">{{Cite web|url=https://semiengineering.com/racing-to-107nm/|title=The Race To 10/7nm|first=Mark|last=LaPedus|date=May 22, 2017|website=Semiconductor Engineering}}</ref>