Editing Peripheral Component Interconnect (section)

===PCI address spaces===
PCI has three address spaces: memory, I/O address, and configuration.

Memory addresses are 32&nbsp;bits (optionally 64 bits) in size, support [[cache (computing)|caching]] and can be burst transactions.

I/O addresses are for compatibility with the Intel [[x86 architecture]]'s I/O port address space. Although the PCI bus specification allows burst transactions in any address space, most devices only support it for memory addresses and not I/O.

Finally, [[PCI configuration space]] provides access to 256 bytes of special configuration registers per PCI device.  Each PCI slot gets its own configuration space address range. The registers are used to configure devices memory and I/O address ranges they should respond to from transaction initiators.  When a computer is first turned on, all PCI devices respond only to their configuration space accesses. The computer's BIOS scans for devices and assigns Memory and I/O address ranges to them.

If an address is not claimed by any device, the transaction initiator's address phase will time out causing the initiator to abort the operation.  In case of reads, it is customary to supply all-ones for the read data value (0xFFFFFFFF) in this case. PCI devices therefore generally attempt to avoid using the all-ones value in important status registers, so that such an error can be easily detected by software.