Editing PDP-8 (section)

====Group 1====
<pre>
        00 01 02 03 04 05 06 07 08 09 10 11
        ___________________________________
       | 1| 1| 1| 0|  |  |  |  |  |  |  |  |
       |__|__|__|__|__|__|__|__|__|__|__|__|
                   |CLA   CMA   RAR   BSW
                       CLL   CML   RAL   IAC

    Execution order  1  1  2  2  4  4  4  3
</pre>
:7200 – CLA – Clear Accumulator
:7100 – CLL – Clear the L Bit
:7040 – CMA – Ones Complement Accumulator
:7020 – CML – Complement L Bit
:7001 – IAC – Increment <L,AC>
:7010 – RAR – Rotate <L,AC> Right
:7004 – RAL – Rotate <L,AC> Left
:7012 – RTR – Rotate <L,AC> Right Twice
:7006 – RTL – Rotate <L,AC> Left Twice
:7002 – BSW – Byte Swap 6-bit "bytes" (PDP 8/e and up)

In most cases, the operations are sequenced so that they can be combined in the most useful ways. For example, combining CLA (CLear Accumulator), CLL (CLear Link), and IAC (Increment ACcumulator) first clears the AC and Link, then increments the accumulator, leaving it set to 1. Adding RAL to the mix (so CLA CLL IAC RAL) causes the accumulator to be cleared, incremented, then rotated left, leaving it set to 2. In this way, small integer constants were placed in the accumulator with a single instruction.

The combination CMA IAC, which the assembler lets you abbreviate as CIA, produces the arithmetic inverse of AC: the twos-complement negation. Since there is no subtraction instruction, only the twos-complement add (TAD), computing the difference of two operands, requires first negating the subtrahend.

A Group 1 OPR instruction that has none of the microprogrammed bits set performs no action. The programmer can write [[NOP (code)|NOP]] (No Operation) to assemble such an instruction.