Editing Motorola 68000 (section)

==Architecture==
{| class="infobox" style="font-size:88%;width:39em;"
|-
|+ Motorola 68000 registers
|-
|
{| style="font-size:88%;"
|-
| style="width:10px; text-align:left"  | <sup>3</sup><sub>1</sub>
| style="width:60px; text-align:center"| ...
| style="width:10px; text-align:right" | <sup>2</sup><sub>3</sub>
| style="width:60px; text-align:center"| ...
| style="width:10px; text-align:center"| <sup>1</sup><sub>5</sub>
| style="width:60px; text-align:center"| ...
| style="width:10px; text-align:center"| <sup>0</sup><sub>7</sub>
| style="width:60px; text-align:center"| ...
| style="width:10px; text-align:center"| <sup>0</sup><sub>0</sub>
| style="width:auto; background:white; color:black" | ''(bit position)''
|-
|colspan="10" | '''Data registers'''
|- style="background:silver;color:black"
| style="text-align:center;" colspan="9"| D0
| style="background:white; color:black" | Data 0
|- style="background:silver;color:black"
| style="text-align:center;" colspan="9"| D1
| style="background:white; color:black" | Data 1
|- style="background:silver;color:black"
| style="text-align:center;" colspan="9"| D2
| style="background:white; color:black" | Data 2
|- style="background:silver;color:black"
| style="text-align:center;" colspan="9"| D3
| style="background:white; color:black" | Data 3
|- style="background:silver;color:black"
| style="text-align:center;" colspan="9"| D4
| style="background:white; color:black" | Data 4
|- style="background:silver;color:black"
| style="text-align:center;" colspan="9"| D5
| style="background:white; color:black" | Data 5
|- style="background:silver;color:black"
| style="text-align:center;" colspan="9"| D6
| style="background:white; color:black" | Data 6
|- style="background:silver;color:black"
| style="text-align:center;" colspan="9"| D7
| style="background:white; color:black" | Data 7
|-
|colspan="10" | '''Address registers'''
|- style="background:silver;color:black"
| style="text-align:center" colspan="2" | &nbsp;
| style="text-align:center;padding-right:18%" colspan="7"| A0
| style="background:white; color:black" | Address 0
|- style="background:silver;color:black"
| style="text-align:center" colspan="2" | &nbsp;
| style="text-align:center;padding-right:18%" colspan="7"| A1
| style="background:white; color:black" | Address 1
|- style="background:silver;color:black"
| style="text-align:center" colspan="2" | &nbsp;
| style="text-align:center;padding-right:18%" colspan="7"| A2
| style="background:white; color:black" | Address 2
|- style="background:silver;color:black"
| style="text-align:center" colspan="2" | &nbsp;
| style="text-align:center;padding-right:18%" colspan="7"| A3
| style="background:white; color:black" | Address 3
|- style="background:silver;color:black"
| style="text-align:center" colspan="2" | &nbsp;
| style="text-align:center;padding-right:18%" colspan="7"| A4
| style="background:white; color:black" | Address 4
|- style="background:silver;color:black"
| style="text-align:center" colspan="2" | &nbsp;
| style="text-align:center;padding-right:18%" colspan="7"| A5
| style="background:white; color:black" | Address 5
|- style="background:silver;color:black"
| style="text-align:center" colspan="2" | &nbsp;
| style="text-align:center;padding-right:18%" colspan="7"| A6
| style="background:white; color:black" | Address 6
|-
|colspan="10" | '''Stack pointers'''
|- style="background:silver;color:black"
| style="text-align:center" colspan="2"| &nbsp;
| style="text-align:center;padding-right:18%" colspan="7"| A7 / USP
| style="background:white; color:black;"| Stack&nbsp;Pointer (user)
|- style="background:silver;color:black"
| style="text-align:center" colspan="2"| &nbsp;
| style="text-align:center;padding-right:18%" colspan="7"| A7' / SSP
| style="background:white; color:black;"| Stack&nbsp;Pointer (supervisor)
|-
|colspan="10" | '''Program counter'''
|- style="background:silver;color:black"
| style="text-align:center" colspan="2"| &nbsp;
| style="text-align:center;padding-right:18%" colspan="7"| PC
| style="background:white; color:black;"| Program&nbsp;Counter
|}
|-
|
{| style="font-size:88%;"
|-
|colspan="17" | '''Condition Code Register'''
|-
| style="width:98px; text-align:center"| &nbsp;
| style="width:10px; text-align:center"| <sup>1</sup><sub>5</sub>
| style="width:10px; text-align:center"| <sup>1</sup><sub>4</sub>
| style="width:10px; text-align:center"| <sup>1</sup><sub>3</sub>
| style="width:10px; text-align:center"| <sup>1</sup><sub>2</sub>
| style="width:10px; text-align:center"| <sup>1</sup><sub>1</sub>
| style="width:10px; text-align:center"| <sup>1</sup><sub>0</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>9</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>8</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>7</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>6</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>5</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>4</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>3</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>2</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>1</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>0</sub>
| style="width:auto; background:white; color:black" | ''(bit position)''
|- style="background:silver;color:black"
| style="background:white;"| &nbsp;
| style="text-align:center" colspan="2"| T
| style="text-align:center"| S
| style="text-align:center"| M
| style="text-align:center"| 0
| style="text-align:center" colspan="3"| I
| style="text-align:center"| 0
| style="text-align:center"| 0
| style="text-align:center"| 0
| style="text-align:center"| X
| style="text-align:center"| [[Sign flag|N]]
| style="text-align:center"| [[Zero flag|Z]]
| style="text-align:center"| [[Overflow flag|V]]
| style="text-align:center"| [[Carry flag|C]]
| style="background:white; color:black" | '''CCR'''
|}
|}

===Address bus===
The 68000 has a 24-bit external address bus and two byte-select signals "replaced" A0. These 24 lines can therefore address 16 MB of physical memory with byte resolution. Address storage and computation uses 32 bits internally; however, the 8 high-order address bits are ignored due to the physical lack of device pins. This allows it to run software written for a logically flat 32-bit [[address space]], while accessing only a 24-bit physical address space. <!-- "By modern definition (ref?) this meant that the 68000 was a 32-bit microprocessor." That means an 8080 or 6809 is a 16-bit processor? Most definitions of bitness use internal bus size or instruction types.  The 68000 used unparalleled 16 bit internal bus and 3 16-bit ALU: 2 ALUs for Data Registers and 1 ALU for Addresses.--><!-- The 68000 could be described as 32/32-bit CPU, having 32-bit registers and a 32-bit logical address space; likewise, the 8080 is an 8/16-bit (or 8/16/16-bit) CPU, and the 6502/6800/6809 are 8/16-bit CPUs. --> Motorola's intent with the internal 32-bit address space was forward compatibility, making it feasible to write 68000 software that would take full advantage of later 32-bit implementations of the 68000 instruction set.<ref name="Starnes" />

However, this did not prevent programmers from writing forward incompatible software. "24-bit" software that discarded the upper address byte, or used it for purposes other than addressing, could fail on 32-bit 68000 implementations. For example, early (pre-7.0) versions of Apple's [[Classic Mac OS|Mac OS]] used the high byte of memory-block master pointers to hold flags such as ''locked'' and ''purgeable''. Later versions of the OS moved the flags to a nearby location, and Apple began shipping computers which had "[[32-bit clean]]" ROMs beginning with the release of the 1989 Mac IIci.

The 68000 family stores multi-byte integers in memory in [[endianness|big-endian]] order.

===Internal registers===
The [[Central processing unit|CPU]] has eight 32-bit general-purpose data [[processor register|registers]] (D0-D7), and eight address registers (A0-A7). The last address register is the [[stack (data structure)|stack pointer]], and assemblers accept the label SP as equivalent to A7. This was a good number of registers at the time in many ways. It was small enough to allow the 68000 to respond quickly to [[interrupt]]s (even in the worst case where all 8 data registers D0–D7 and 7 address registers A0–A6 needed to be saved, 15 registers in total), and yet large enough to make most calculations fast, because they could be done entirely within the processor without keeping any partial results in memory. (Note that an exception routine in supervisor mode can also save the user stack pointer A7, which would total 8 address registers. However, the dual stack pointer (A7 and supervisor-mode A7') design of the 68000 makes this normally unnecessary, except when a task switch is performed in a multitasking system.)

Having the two types of registers allows one 32-bit address and one 16-bit data calculation to take place at the same time. This results in reduced instruction execution time as addresses and data can be processed in parallel.<ref name="Starnes" />

===Status register===
The 68000 has a 16-bit status register. The upper 8 bits is the system byte, and modification of it is privileged. The lower 8 bits is the user byte, also known as the condition code register (CCR), and modification of it is not privileged. The 68000 comparison, arithmetic, and logic operations modify condition codes to record their results for use by later conditional jumps. The condition code bits are "carry" (C), "overflow" (V), "zero" (Z), "negative" (N) and "extend" (X). The "extend" (X) flag deserves special mention, because it is separate from the [[carry flag]]. This permits the extra bit from arithmetic, logic, and shift operations to be separated from the carry [[multiprecision arithmetic]].<ref>{{cite book|url=https://books.google.com/books?id=2BUEEgvMcyUC&pg=PA149|title=Assembly Language and Systems Programming for the M68000 Family|edition=Second|last1=Ford|first1=William|last2=Topp|first2=William R.|publisher=[[Jones and Bartlett Publishers]]|date=1997|access-date=2022-07-29|pages=149–151|isbn=0-7637-0357-5|archive-date=July 29, 2022|archive-url=https://web.archive.org/web/20220729234028/https://books.google.com/books?id=2BUEEgvMcyUC&pg=PA149|url-status=live}}</ref>

===Instruction set===
The designers attempted to make the assembly language [[Orthogonal instruction set|orthogonal]]. That is, instructions are divided into operations and [[Addressing mode|address modes]], and almost all address modes are available for almost all instructions. There are 56 instructions and a minimum instruction size of 16 bits. Many instructions and addressing modes are longer to include more address or mode bits.

===Privilege levels===
The CPU, and later the whole family, implements two levels of privilege. User mode gives access to everything except privileged instructions such as interrupt level controls.<ref name=":0">{{cite book |year=1993 |url=https://www.nxp.com/docs/en/reference-manual/MC68000UM.pdf |title=M68000 8-/16-/32-Bit Microprocessors User's Manual Ninth Edition |publisher=Motorola |at=p. 6-2 |access-date=February 28, 2022 |archive-date=April 14, 2022 |archive-url=https://web.archive.org/web/20220414231314/https://www.nxp.com/docs/en/reference-manual/MC68000UM.pdf |url-status=live }}</ref> Supervisor privilege gives access to everything. An interrupt always becomes supervisory. The supervisor bit is stored in the status register, and is visible to user programs.<ref name=":0" />

An advantage of this system is that the supervisor level has a separate stack pointer. This permits a [[computer multitasking|multitasking]] system to use very small stacks for tasks, because the designers do not have to allocate the memory required to hold the stack frames of a maximum stack-up of interrupts.

===Interrupts===<!-- This section is linked from [[Guru Meditation]] -->
The CPU recognizes seven [[interrupt]] levels. Levels 1 through 5 are strictly prioritized. That is, a higher-numbered interrupt can always interrupt a lower-numbered interrupt. In the status register, a privileged instruction allows setting the current minimum interrupt level, blocking lower or equal priority interrupts. For example, if the interrupt level in the status register is set to 3, higher levels from 4 to 7 can cause an exception. Level 7 is a level triggered [[non-maskable interrupt]] (NMI). Level 1 can be interrupted by any higher level. Level 0 means no interrupt. The level is stored in the status register, and is visible to user-level programs.

Hardware interrupts are signalled to the CPU using three inputs that encode the highest pending interrupt priority. A separate encoder is usually required to encode the interrupts, though for systems that do not require more than three hardware interrupts it is possible to connect the interrupt signals directly to the encoded inputs at the cost of more software complexity. The interrupt controller can be as simple as a [[7400-series integrated circuits|74LS148]] priority encoder, or may be part of a [[Very Large Scale Integration|very large-scale integration]] (VLSI) peripheral chip such as the MC68901 Multi-Function Peripheral (used in the [[Atari ST]] range of computers and [[X68000]]), which also provides a [[UART]], timer, and parallel I/O.

The "exception table" ([[interrupt vector table]] interrupt vector addresses) is fixed at addresses 0 through 1023, permitting 256 32-bit vectors. The first vector (RESET) consists of two vectors, namely the starting stack address, and the starting code address. Vectors 3 through 15 are used to report various errors: [[bus error]], address error, [[illegal instruction]], [[zero division]], CHK and CHK2 vector, privilege violation (to block [[privilege escalation]]), and some reserved vectors that became line 1010 emulator, line 1111 emulator, and hardware [[breakpoint]]. Vector 24 starts the '''real''' interrupts: [[spurious interrupt]] (no hardware acknowledgement), and level 1 through level 7 autovectors, then the 16&nbsp;TRAP vectors, then some more reserved vectors, then the user defined vectors.

Since the starting code address vector must always be valid on reset, systems commonly included some nonvolatile memory (e.g. [[Read-only memory|ROM]]) starting at address zero to contain the vectors and [[booting|bootstrap]] code. However, for a general purpose system it is desirable for the operating system to be able to change the vectors at runtime. This was often accomplished by either pointing the vectors in ROM to a [[Branch table|jump table]] in [[Random Access Memory|RAM]], or through use of [[bank switching]] to allow the ROM to be replaced by RAM at runtime.

The 68000 does not meet the [[Popek and Goldberg virtualization requirements]] for full processor virtualization because it has a single unprivileged instruction, "MOVE from SR", which allows user-mode software read-only access to a small amount of privileged state. The 68EC000 and 68SEC000, which are later derivatives of the 68000, do meet the requirements as the "MOVE from SR" instruction is privileged. The same change was introduced on the 68010 and later CPUs.

The 68000 is also unable to easily support [[virtual memory]], which requires the ability to trap and recover from a failed memory access. The 68000 does provide a bus error exception which can be used to trap, but it does not save enough processor state to resume the faulted instruction once the operating system has handled the exception. Several companies did succeed in making 68000-based Unix workstations with virtual memory that worked by using two 68000 chips running in parallel on different phased clocks. When the "leading" 68000 encountered a bad memory access, extra hardware would interrupt the "main" 68000 to prevent it from also encountering the bad memory access. This interrupt routine would handle the virtual memory functions and restart the "leading" 68000 in the correct state to continue properly synchronized operation when the "main" 68000 returned from the interrupt.

These problems were fixed in the next major revision of the 68k architecture with the release of the MC68010. The Bus Error and Address Error exceptions push a large amount of internal state onto the supervisor stack in order to facilitate recovery, and the "MOVE from SR" instruction was made privileged. A new unprivileged "MOVE from CCR" instruction is provided for use in its place by user mode software; an operating system can trap and emulate user mode "MOVE from SR" instructions if desired.