Editing Memory management unit (section)

=== DEC Alpha ===
[[DEC Alpha]] processors divide memory into {{nowrap|8 KB}}, {{nowrap|16 KB}}, {{nowrap|32 KB}}, or {{nowrap|64 KB}}; the page size is dependent on the processor.<ref name="alpha-axp-arch-manual-openvms">{{cite book |url=http://bitsavers.org/pdf/dec/alpha/Sites_AlphaAXPArchitectureReferenceManual_2ed_1995.pdf |title=Alpha AXP Architecture |chapter=Part II-A / OpenVMS AXP Software |year=1995 |edition=Second |id=EY-TI32E-DP |publisher=[[Digital Press]] |isbn=1-55558-145-5}}</ref>{{rp|pages=3{{hyp}}2}}<ref name="alpha-axp-arch-manual-osf1">{{cite book |url=http://bitsavers.org/pdf/dec/alpha/Sites_AlphaAXPArchitectureReferenceManual_2ed_1995.pdf |title=Alpha AXP Architecture |chapter=Part II-B / DEC OSF/1 Software |year=1995 |edition=Second |id=EY-TI32E-DP |publisher=[[Digital Press]] |isbn=1-55558-145-5}}</ref>{{rp|pages=3{{hyp}}2}} pages.  After a TLB miss, low-level [[firmware]] machine code (here called [[PALcode]]) walks a page table.

The [[OpenVMS]] AXP PALcode and [[DEC OSF/1]] PALcode walk a three-level tree-structured page table.  Addresses are broken down into an unused set of bits (containing the same value as the uppermost bit of the index into the root level of the tree), a set of bits to index the root level of the tree, a set of bits to index the middle level of the tree, a set of bits to index the leaf level of the tree, and remaining bits that pass through to the physical address without modification, indexing a byte within the page.  The sizes of the fields are dependent on the page size; all three tree index fields are the same size.<ref name="alpha-axp-arch-manual-openvms" />{{rp|pages=3{{hyp}}2-3{{hyp}}3}}<ref name="alpha-axp-arch-manual-osf1" />{{rp|pages=3{{hyp}}1-3{{hyp}}2}} The OpenVMS AXP PALcode supports full read and write permission bits for user, supervisor, executive, and kernel modes, and also supports fault on read/write/execute bits are also supported.<ref name="alpha-axp-arch-manual-openvms" />{{rp|pages=3{{hyp}}3-3{{hyp}}6}} The DEC OSF/1 PALcode supports full read and write permission bits for user and kernel modes, and also supports fault on read/write/execute bits are also supported.<ref name="alpha-axp-arch-manual-osf1" />{{rp|pages=(II-B) 3{{hyp}}3-3{{hyp}}6}}

The [[Windows NT]] AXP PALcode can either walk a single-level page table in a virtual address space or a two-level page table in physical address space.  The upper 32 bits of an address are ignored.
For a single-level page table, addresses are broken down into a set of bits to index the page table and remaining bits that pass through to the physical address without modification, indexing a byte within the page.
For a two-level page table, addresses are broken down into a set of bits to index the root level of the tree, a set of bits to index the top level of the tree, a set of bits to index the leaf level of the tree, and remaining bits that pass through to the physical address without modification, indexing a byte within the page.  The sizes of the fields are dependent on the page size.<ref name="alpha-axp-arch-manual-nt">{{cite book |url=http://bitsavers.org/pdf/dec/alpha/Sites_AlphaAXPArchitectureReferenceManual_2ed_1995.pdf |title=Alpha AXP Architecture |chapter=Part II-C / Windows NT AXP Software |year=1995 |edition=Second |id=EY-TI32E-DP |publisher=[[Digital Press]] |isbn=1-55558-145-5}}</ref>{{rp|pages=3{{hyp}}2-3{{hyp}}4}} The Windows NT AXP PALcode supports a page being accessible only from kernel mode or being accessible from user and kernel mode, and also supports a fault on write bit.<ref name="alpha-axp-arch-manual-nt" />{{rp|page=3{{hyp}}5}}