Editing Make (software) (section)

==Examples==

The following commands are in the context of the makefile that follows.

<syntaxhighlight lang="bash">
make            # updates first target, 'all'
make help       # updates target 'help' to list targets
make dist       # updates target 'dist' to build for distribution
</syntaxhighlight>

<syntaxhighlight lang="make">
PACKAGE	 = package
VERSION	 = ` date "+%Y.%m%d%" `
RELEASE_DIR  = ..
RELEASE_FILE = $(PACKAGE)-$(VERSION)

# Default target
# note: variable LOGNAME comes from the environment
all:
	echo "Hello $(LOGNAME), nothing to do by default"
	echo "Try 'make help'"

# Display targets by searching this file
help:
	egrep "^# target:" [Mm]akefile

# Make a release
dist:
	tar -cf  $(RELEASE_DIR)/$(RELEASE_FILE) && \
	gzip -9  $(RELEASE_DIR)/$(RELEASE_FILE).tar
</syntaxhighlight>

Below is a simple makefile that by default (the "all" rule is listed first) compiles a source file called "helloworld.c" using the system's C compiler and also provides a "clean" target to remove the generated files if the user desires to start over. The {{code|$@}} and {{code|$<}} are two of the so-called internal macros (also known as automatic variables) and stand for the target name and "implicit" source, respectively. In the example below, {{code|$^}} expands to a space delimited list of the prerequisites. There are a number of other internal macros.<ref name=posix-macros /><ref>[https://www.gnu.org/software/make/manual/html_node/Automatic-Variables.html#Automatic-Variables Automatic Variables] {{webarchive |url=https://web.archive.org/web/20160425225736/https://www.gnu.org/software/make/manual/html_node/Automatic-Variables.html#Automatic-Variables |date=April 25, 2016 }} GNU `make'</ref>

<syntaxhighlight lang="make">
CFLAGS ?= -g

all: helloworld

helloworld: helloworld.o
	$(CC) $(LDFLAGS) -o $@ $^

helloworld.o: helloworld.c
	$(CC) $(CFLAGS) -c -o $@ $<

clean:
	$(RM) helloworld helloworld.o
</syntaxhighlight>

Many systems<!--
at least open group base specification compliant systems, see above ref
--> come with predefined Make rules and macros to specify common tasks such as compilation based on file suffix.  This lets users omit the actual (often unportable) instructions of how to generate the target from the source(s). On such a system the makefile above could be modified as follows:

<syntaxhighlight lang="make">
all: helloworld

helloworld: helloworld.o
	$(CC) $(CFLAGS) $(LDFLAGS) -o $@ $^

clean:
	$(RM) helloworld helloworld.o

# suffix rule
.c.o:
	$(CC) $(CFLAGS) -c $<

.SUFFIXES: .c
</syntaxhighlight>

<!--
it appears that the open group base specification says .SUFFIXES and simple suffix
rules must work, so there, gnu make.
-->

That "helloworld.o" depends on "helloworld.c" is now automatically handled by Make. In such a simple example as the one illustrated here this hardly matters, but the real power of suffix rules becomes evident when the number of source files in a software project starts to grow. One only has to write a rule for the linking step and declare the object files as prerequisites. Make will then implicitly determine how to make all the object files and look for changes in all the source files.

Simple suffix rules work well as long as the source files do not depend on each other and on other files such as header files. Another route to simplify the build process is to use so-called pattern matching rules that can be combined with compiler-assisted dependency generation. As a final example requiring the gcc compiler and GNU Make, here is a generic makefile that compiles all C files in a folder to the corresponding object files and then links them to the final executable. Before compilation takes place, dependencies are gathered in makefile-friendly format into a hidden file ".depend" that is then included to the makefile.  Portable programs ought to avoid constructs used below.

<syntaxhighlight lang="make">
# Generic GNUMakefile

# snippet to fail if not GNU
ifneq (,)
This makefile requires GNU Make.
endif

PROGRAM = foo
C_FILES := $(wildcard *.c)
OBJS := $(patsubst %.c, %.o, $(C_FILES))
CC = cc
CFLAGS = -Wall -pedantic
LDFLAGS =
LDLIBS = -lm

all: $(PROGRAM)

$(PROGRAM): .depend $(OBJS)
	$(CC) $(CFLAGS) $(OBJS) $(LDFLAGS) -o $(PROGRAM) $(LDLIBS)

depend: .depend

.depend: cmd = gcc -MM -MF depend $(var); cat depend >> .depend;
.depend:
	@echo "Generating dependencies..."
	@$(foreach var, $(C_FILES), $(cmd))
	@rm -f depend

-include .depend

# These are the pattern matching rules. In addition to the automatic
# variables used here, the variable $* that matches whatever % stands for
# can be useful in special cases.
%.o: %.c
	$(CC) $(CFLAGS) -c $< -o $@

%: %.o
	$(CC) $(CFLAGS) -o $@ $<

clean:
	rm -f .depend $(OBJS)

.PHONY: clean depend

</syntaxhighlight>