Editing MIPS architecture (section)

=== MIPS32/MIPS64 ===

The first release of MIPS32, based on MIPS II, added conditional moves, [[Instruction prefetch|prefetch instructions]], and other features from the R4000 and R5000 families of 64-bit processors.<ref name="mips32-and-mips64"/> The first release of MIPS64 adds a MIPS32 mode to run 32-bit code.<ref name="mips32-and-mips64"/> The MUL and MADD ([[multiply-add]]) instructions, previously available in some implementations, were added to the MIPS32 and MIPS64 specifications, as were [[cache control instruction]]s.<ref name="mips32-and-mips64"/> For the purpose of cache control, both <code>SYNC</code> and <code>SYNCI</code> instructions were prepared.<ref>{{Cite web |url=https://training.mips.com/basic_mips/PDF/Instruction_Set.pdf |title=MIPS instruction set R5 |page=59-62 |accessdate=2023-12-15 |archive-date=December 15, 2023 |archive-url=https://web.archive.org/web/20231215041747/https://training.mips.com/basic_mips/PDF/Instruction_Set.pdf |url-status=live }}</ref><ref>{{Cite web |url=https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00605-2B-CMPCOHERE-AFP-01.01.pdf |title=MIPS® Coherence Protocol Specification, Revision 01.01 |page=26,25,57 |accessdate=2023-12-15 |archive-date=September 4, 2018 |archive-url=https://web.archive.org/web/20180904050625/https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00605-2B-CMPCOHERE-AFP-01.01.pdf |url-status=live }}</ref>

MIPS32/MIPS64 Release 6 in 2014 added the following:<ref>{{cite web|url=https://imgtec.com/mips/architectures/mips32/|title=MIPS – Market-leading RISC CPU IP processor solutions|website=imgtec.com|url-status=dead|archive-url=https://web.archive.org/web/20160309061723/https://imgtec.com/mips/architectures/mips32/|archive-date=March 9, 2016|access-date=February 11, 2016}}</ref>
* a new family of branches with no delay slot:
** unconditional branches (BC) and branch-and-link (BALC) with a 26-bit offset,
** conditional branch on zero/non-zero with a 21-bit offset,
** full set of signed and unsigned conditional branches compare between two registers (e.g. BGTUC) or a register against zero (e.g. BGTZC),
** full set of branch-and-link which compare a register against zero (e.g. BGTZALC).
* index jump instructions with no delay slot designed to support large absolute addresses.
* instructions to load 16-bit immediates at bit position 16, 32 or 48, allowing to easily generate large constants.
* PC-relative load instructions, as well as address generation with large (PC-relative) offsets.
* bit-reversal and byte-alignment instructions (previously only available with the DSP extension).
* multiply and divide instructions redefined so that they use a single register for their result).
* instructions generating truth values now generate all zeroes or all ones instead of just clearing/setting the 0-bit,
* instructions using a truth value now only interpret all-zeroes as false instead of just looking at the 0-bit.

Removed infrequently used instructions:
* some conditional moves
* ''branch likely'' instructions (deprecated in previous releases).
* integer overflow trapping instructions with 16-bit immediate
* integer accumulator instructions (together HI/LO registers, moved to the DSP Application-Specific Extension)
* unaligned load instructions (LWL and LWR), (requiring that most ordinary loads and stores support misaligned access, possibly via trapping and with the addition of a new instruction (BALIGN))

Reorganized the instruction encoding, freeing space for future expansions.