Editing Field-programmable gate array (section)

=== 3D architectures ===
To shrink the size and power consumption of FPGAs, vendors such as [[Tabula (company)|Tabula]] and [[Xilinx]] have introduced [[three-dimensional integrated circuit|3D or stacked architectures]].<ref>Dean Takahashi, VentureBeat. "[https://venturebeat.com/2011/05/02/intel-connection-helped-chip-startup-tabula-raise-108m Intel connection helped chip startup Tabula raise $108M]." May 2, 2011. Retrieved May 13, 2011.</ref><ref name="lawrence">Lawrence Latif, The Inquirer. "[https://web.archive.org/web/20101029124903/http://www.theinquirer.net/inquirer/news/1811460/fpga-manufacturer-claims-beat-moores-law FPGA manufacturer claims to beat Moore's Law]." October 27, 2010. Retrieved May 12, 2011.</ref> Following the introduction of its [[28 nm|28&nbsp;nm]] 7-series FPGAs, Xilinx said that several of the highest-density parts in those FPGA product lines will be constructed using multiple dies<!--dice or dies is correct for integrated circuits&nbsp;— Wiktionary--> in one package, employing technology developed for 3D construction and stacked-die assemblies.

Xilinx's approach stacks several (three or four) active FPGA dies side by side on a silicon [[interposer]]&nbsp;– a single piece of silicon that carries passive interconnect.<ref name="lawrence" /><ref>EDN Europe. "[http://www.edn-europe.com/xilinxadoptsstackeddie3dpackaging+article+4461+Europe.html Xilinx adopts stacked-die 3D packaging] {{Webarchive|url=https://web.archive.org/web/20110219182606/http://www.edn-europe.com/xilinxadoptsstackeddie3dpackaging+article+4461+Europe.html |date=2011-02-19 }}." November 1, 2010. Retrieved May 12, 2011.</ref> The multi-die construction also allows different parts of the FPGA to be created with different process technologies, as the process requirements are different between the FPGA fabric itself and the very high speed 28&nbsp;Gbit/s serial transceivers. An FPGA built in this way is called a ''[[Heterogeneous computing|heterogeneous]] FPGA''.<ref>{{Cite web|url=https://www.xilinx.com/support/documentation/white_papers/wp380_Stacked_Silicon_Interconnect_Technology.pdf |archive-url=https://web.archive.org/web/20101105113516/http://www.xilinx.com/support/documentation/white_papers/wp380_Stacked_Silicon_Interconnect_Technology.pdf |archive-date=2010-11-05 |url-status=live|title=Xilinx Stacked Silicon Interconnect Technology Delivers Breakthrough FPGA Capacity, Bandwidth, and Power Efficiency|last=Saban|first=Kirk|date=December 11, 2012|website=xilinx.com|access-date=2018-11-30}}</ref>

Altera's heterogeneous approach involves using a single monolithic FPGA die and connecting other dies and technologies to the FPGA using Intel's embedded multi_die interconnect bridge (EMIB) technology.<ref>{{cite web|url=http://www.intel.com/content/www/us/en/foundry/emib.html|title=Intel Custom Foundry EMIB|work=Intel|access-date=2015-07-13|archive-date=2015-07-13|archive-url=https://web.archive.org/web/20150713230215/http://www.intel.com/content/www/us/en/foundry/emib.html|url-status=dead}}</ref>