Editing Dynamic random-access memory (section)

===Historical cell designs===
First-generation DRAM ICs (those with capacities of 1&nbsp;Kbit), such as the archetypical [[Intel 1103]], used a three-transistor, one-capacitor (3T1C) DRAM cell with separate read and write circuitry.  The write wordline drove a write transistor which connected the capacitor to the write bitline just as in the 1T1C cell, but there was a separate read wordline and read transistor which connected an amplifier transistor to the read bitline.  By the second generation, the drive to reduce cost by fitting the same amount of bits in a smaller area led to the almost universal adoption of the 1T1C DRAM cell, although a couple of devices with 4 and 16&nbsp;Kbit capacities continued to use the 3T1C cell for performance reasons (Kenner, p.&nbsp;6). These performance advantages included, most significantly, the ability to read the state stored by the capacitor without discharging it, avoiding the need to write back what was read out (non-destructive read). A second performance advantage relates to the 3T1C cell's separate transistors for reading and writing; the memory controller can exploit this feature to perform atomic read-modify-writes, where a value is read, modified, and then written back as a single, indivisible operation (Jacob, p.&nbsp;459).