Editing Digital electronics (section)

===Automated design tools===
{{Unreferenced section|date=June 2021}}
Much of the effort of designing large logic machines has been automated through the application of [[electronic design automation]] (EDA).

Simple truth table-style descriptions of logic are often optimized with EDA that automatically produce reduced systems of logic gates or smaller lookup tables that still produce the desired outputs. The most common example of this kind of software is the [[Espresso heuristic logic minimizer]]. Optimizing large logic systems may be done using the [[Quine–McCluskey algorithm]] or [[binary decision diagram]]s. There are promising experiments with [[genetic algorithm]]s and [[Simulated annealing|annealing optimization]]s.

To automate costly engineering processes, some EDA can take [[state table]]s that describe [[state machine]]s and automatically produce a truth table or a [[function table]] for the [[combinational logic]] of a state machine. The state table is a piece of text that lists each state, together with the conditions controlling the transitions between them and their associated output signals.

Often, real logic systems are designed as a series of sub-projects, which are combined using a ''tool flow''. The tool flow is usually controlled with the help of a [[scripting language]], a simplified computer language that can invoke the software design tools in the right order. Tool flows for large logic systems such as [[microprocessor]]s can be thousands of commands long, and combine the work of hundreds of engineers. Writing and debugging tool flows is an established engineering specialty in companies that produce digital designs. The tool flow usually terminates in a detailed computer file or set of files that describe how to physically construct the logic. Often it consists of instructions on how to draw the [[transistor]]s and wires on an integrated circuit or a [[printed circuit board]].

Parts of tool flows are debugged by verifying the outputs of simulated logic against expected inputs. The test tools take computer files with sets of inputs and outputs and highlight discrepancies between the simulated behavior and the expected behavior. Once the input data is believed to be correct, the design itself must still be verified for correctness. Some tool flows verify designs by first producing a design, then scanning the design to produce compatible input data for the tool flow. If the scanned data matches the input data, then the tool flow has probably not introduced errors.

The functional [[Formal verification|verification]] data are usually called ''test vectors''. The functional test vectors may be preserved and used in the factory to test whether newly constructed logic works correctly. However, functional test patterns do not discover all fabrication faults. Production tests are often designed by [[automatic test pattern generation]] software tools. These generate test vectors by examining the structure of the logic and systematically generating tests targeting particular potential faults. This way the [[fault coverage]] can closely approach 100%, provided the design is properly made testable (see next section).

Once a design exists, and is verified and testable, it often needs to be processed to be manufacturable as well. Modern integrated circuits have features smaller than the wavelength of the light used to expose the photoresist. Software that are [[Design for manufacturability|designed for manufacturability]] add interference patterns to the exposure masks to eliminate open-circuits and enhance the masks' contrast.