Editing X86 (section)

===16-bit===
The original [[Intel 8086]] and [[Intel 8088|8088]] have fourteen 16-[[bit]] registers. Four of them (AX, BX, CX, DX) are general-purpose registers (GPRs), although each may have an additional purpose; for example, only CX can be used as a counter with the loop instruction. Each can be accessed as two separate bytes (thus BX's high byte can be accessed as BH and low byte as BL). Two pointer registers have special roles: SP (stack pointer) points to the "top" of the [[stack (data structure)|stack]], and BP (base pointer) is often used to point at some other place in the stack, typically above the local variables (see [[frame pointer]]). The registers SI, DI, BX and BP are [[address register]]s, and may also be used for array indexing.

One of four possible 'segment registers' (CS, DS, SS and ES) is used to form a memory address. In the original 8086 / 8088 / 80186 / 80188 every address was built from a segment register and one of the general purpose registers. For example ds:si is the notation for an address formed as [16 * ds + si] to allow 20-bit addressing rather than 16 bits, although this changed in later processors. At that time only certain combinations were supported.

The [[FLAGS register (computing)|FLAGS register]] contains [[Flag (computing)|flag]]s such as [[carry flag]], [[overflow flag]] and [[zero flag]]. Finally, the [[instruction pointer]] (IP) points to the next instruction that will be fetched from memory and then executed; this register cannot be directly accessed (read or written) by a program.<ref>{{cite web |url=http://www.cs.virginia.edu/~evans/cs216/guides/x86.html |title=Guide to x86 Assembly |publisher=Cs.virginia.edu |date=September 11, 2013 |access-date=February 6, 2014 |archive-date=March 24, 2020 |archive-url=https://web.archive.org/web/20200324154938/http://www.cs.virginia.edu/~evans/cs216/guides/x86.html |url-status=live }}</ref>

The [[Intel 80186]] and [[Intel 80188|80188]] are essentially an upgraded 8086 or 8088 CPU, respectively, with on-chip peripherals added, and they have the same CPU registers as the 8086 and 8088 (in addition to interface registers for the peripherals).

The 8086, 8088, 80186, and 80188 can use an optional floating-point coprocessor, the [[Intel 8087|8087]]. The 8087 appears to the programmer as part of the CPU and adds eight 80-bit wide registers, st(0) to st(7), each of which can hold numeric data in one of seven formats: 32-, 64-, or 80-bit floating point, 16-, 32-, or 64-bit (binary) integer, and 80-bit packed decimal integer.<ref name="i86"/>{{rp|S-6, S-13..S-15}} It also has its own 16-bit status register accessible through the {{mono|fstsw}} instruction, and it is common to simply use some of its bits for branching by copying it into the normal FLAGS.<ref>{{cite web |title=FSTSW/FNSTSW — Store x87 FPU Status Word |url=https://www.felixcloutier.com/x86/fstsw:fnstsw |quote=The FNSTSW AX form of the instruction is used primarily in conditional branching... |access-date=January 15, 2020 |archive-date=January 25, 2022 |archive-url=https://web.archive.org/web/20220125121653/https://www.felixcloutier.com/x86/fstsw:fnstsw |url-status=live }}</ref>

In the [[Intel 80286]], to support [[protected mode]], three special registers hold descriptor table addresses (GDTR, LDTR, [[Interrupt descriptor table|IDTR]]), and a fourth task register (TR) is used for task switching. The [[Intel 80287|80287]] is the floating-point coprocessor for the 80286 and has the same registers as the 8087 with the same data formats.