Editing VHDL (section)

===D-type flip-flops===
The D-type [[Flip-flop (electronics)|flip-flop]] samples an incoming signal at the rising (or falling) edge of a clock. This example has an asynchronous, active-high reset, and samples at the rising clock edge.
<syntaxhighlight lang="vhdl">
DFF : process(all) is
begin
  if RST then
    Q <= '0';
  elsif rising_edge(CLK) then
    Q <= D;
  end if;
end process DFF;
</syntaxhighlight>

Another common way to write edge-triggered behavior in VHDL is with the 'event' signal attribute. A single apostrophe has to be written between the signal name and the name of the attribute.
<syntaxhighlight lang="vhdl">
DFF : process(RST, CLK) is
begin
  if RST then
    Q <= '0';
  elsif CLK'event and CLK = '1' then
    Q <= D;
  end if;
end process DFF;
</syntaxhighlight>

VHDL also lends itself to "one-liners" such as:
<syntaxhighlight lang="VHDL">
DFF : Q <= '0' when RST = '1' else D when rising_edge(clk);
</syntaxhighlight>

or:

<syntaxhighlight lang="vhdl">
DFF : process(all) is 
begin
  if rising_edge(CLK) then
    Q <= D;
  end if;
  if RST then
    Q <= '0';
  end if;
end process DFF;

</syntaxhighlight>
or:<syntaxhighlight lang="vhdl">
Library IEEE;
USE IEEE.Std_logic_1164.all;

entity RisingEdge_DFlipFlop_SyncReset is
  port(
    Q          :   out std_logic;    
    Clk        : in    std_logic;  
    sync_reset : in    std_logic;  
    D          : in    std_logic    
  );
end RisingEdge_DFlipFlop_SyncReset;

architecture Behavioral of RisingEdge_DFlipFlop_SyncReset is
begin
  process(Clk)
  begin 
    if (rising_edge(Clk)) then
      if (sync_reset='1') then 
        Q <= '0';
      else 
        Q <= D; 
      end if;
    end if;       
  end process;  
end Behavioral;
</syntaxhighlight>Which can be useful if not all signals (registers) driven by this process should be reset.