Editing Semiconductor device fabrication (section)

===Back-end-of-line (BEOL) processing===
{{Main|BEOL}}

====Metal layers====
Once the various semiconductor devices have been [[Integrated circuit#circuitLayers|created]], they must be interconnected to form the desired electrical circuits. This occurs in a series of wafer processing steps collectively referred to as BEOL (not to be confused with ''back end'' of chip fabrication, which refers to the packaging and testing stages). BEOL processing involves creating metal interconnecting wires that are isolated by dielectric layers. The insulating material has traditionally been a form of SiO<sub>2</sub> or a [[silicate glass]], but recently new [[low-κ dielectric|low dielectric constant]] materials, also called low-κ dielectrics, are being used (such as silicon oxycarbide), typically providing dielectric constants around 2.7 (compared to 3.82 for SiO<sub>2</sub>), although materials with constants as low as 2.2 are being offered to chipmakers. 

BEoL has been used since 1995 at the 350nm and 250nm nodes (0.35 and 0.25 micron nodes), at the same time chemical mechanical polishing began to be employed. At the time, 2 metal layers for interconnect, also called metallization<ref>{{cite book | url=https://books.google.com/books?id=nC7wCAAAQBAJ&dq=integrated+circuit+metallization&pg=PA276 | title=Technology of Integrated Circuits | isbn=978-3-662-04160-4 | last1=Widmann | first1=D. | last2=Mader | first2=H. | last3=Friedrich | first3=H. | date=9 March 2013 | publisher=Springer }}</ref> was state-of-the-art.<ref>{{cite web | url=https://www.chiphistory.org/35-beol-origins-the-chip-history-center | title=BEOL Wiring Process for CMOS Logic }}</ref>

Since the 22nm node, some manufacturers have added a new process called middle-of-line (MOL) which connects the transistors to the rest of the interconnect made in the BEoL process. The MOL is often based on tungsten and has upper and lower layers: the lower layer connects the junctions of the transistors, and an upper layer which is a tungsten plug that connects the transistors to the interconnect. Intel at the 10nm node introduced contact-over-active-gate (COAG) which, instead of placing the contact for connecting the transistor close to the gate of the transistor, places it directly over the gate of the transistor to improve transistor density.<ref name="auto7">{{Cite web|url=https://semiengineering.com/racing-to-107nm/|title=The Race To 10/7nm|first=Mark|last=LaPedus|date=May 22, 2017|website=Semiconductor Engineering}}</ref>

====Interconnect====
{{Main| interconnect (integrated circuits) }}
[[Image:Siliconchip by shapeshifter.png|right|thumb|350px|Synthetic detail of a [[standard cell]] through four layers of planarized copper interconnect, down to the polysilicon (pink), wells (greyish) and substrate (green)]]

Historically, the metal wires have been composed '''[[aluminum interconnects|of aluminum]]'''.  In this approach to wiring (often called ''subtractive aluminum''), blanket films of aluminum are deposited first, patterned, and then etched, leaving isolated wires.  Dielectric material is then deposited over the exposed wires.  The various metal layers are interconnected by etching holes (called "''vias")'' in the insulating material and then depositing [[tungsten]] in them with a [[chemical vapor deposition|CVD]] technique using [[tungsten hexafluoride]]; this approach can still be (and often is) used in the fabrication of many memory chips such as [[dynamic random-access memory]] (DRAM), because the number of interconnect levels can be small (no more than four). The aluminum was sometimes alloyed with copper for preventing recrystallization. Gold was also used in interconnects in early chips.<ref>{{cite book | url=https://books.google.com/books?id=jq3cdQd9XpwC&dq=aluminum+silicon+interconnect&pg=PA397 | isbn=978-3-540-43181-7 | title=Chemical-Mechanical Planarization of Semiconductor Materials | date=26 January 2004 | publisher=Springer }}</ref>

More recently, as the number of interconnect levels for logic has substantially increased due to the large number of transistors that are now interconnected in a modern [[microprocessor]], the timing delay in the wiring has become so significant as to prompt a change in wiring material (from aluminum to '''[[copper interconnect]]''' layer)<ref>{{cite book | url=https://books.google.com/books?id=UUFwuIYrSrQC&q=aluminum+replaced+by+copper+interconnect | isbn=978-1-4419-0076-0 | title=Copper Interconnect Technology | date=22 January 2010 | publisher=Springer }}</ref> alongside a change in dielectric material in the interconnect (from silicon dioxides to newer [[low-κ dielectric|low-κ]] insulators).<ref>{{Cite web|url=https://www.researchgate.net/publication/324645796|title=Introduction to Copper / Low-K Interconnects & Electromigration Fundamentals}}</ref><ref>{{Cite book|url=https://onlinelibrary.wiley.com/doi/10.1002/9781119963677.ch1|title=Low- k Materials: Recent Advances|first1=Geraud|last1=Dubois|first2=Willi|last2=Volksen|chapter=Low- ''k'' Materials: Recent Advances |editor-first1=Mikhail R.|editor-last1=Baklanov|editor-first2=Paul S.|editor-last2=Ho|editor-first3=Ehrenfried|editor-last3=Zschech|date=February 24, 2012|publisher=Wiley|pages=1–33|via=CrossRef|doi=10.1002/9781119963677.ch1|isbn=978-0-470-66254-0 }}</ref> This performance enhancement also comes at a reduced cost via [[Copper interconnect#Patterning|damascene]] processing, which eliminates processing steps. As the number of interconnect levels increases, planarization of the previous layers is required to ensure a flat surface prior to subsequent lithography. Without it, the levels would become increasingly crooked, extending outside the depth of focus of available lithography, and thus interfering with the ability to pattern. CMP ([[chemical-mechanical planarization]]) is the primary processing method to achieve such planarization, although dry ''etch back'' is still sometimes employed when the number of interconnect levels is no more than three. Copper interconnects use an electrically conductive barrier layer to prevent the copper from diffusing into ("poisoning") its surroundings, often made of tantalum nitride.<ref>{{cite journal | pmc=7664900 | date=2020 | last1=Li | first1=Z. | last2=Tian | first2=Y. | last3=Teng | first3=C. | last4=Cao | first4=H. | title=Recent Advances in Barrier Layer of Cu Interconnects | journal=Materials | volume=13 | issue=21 | page=5049 | doi=10.3390/ma13215049 | pmid=33182434 | bibcode=2020Mate...13.5049L | doi-access=free }}</ref><ref name="auto7"/> In 1997, IBM was the first to adopt copper interconnects.<ref>{{cite web | url=https://www.chiphistory.org/ibm-s-development-of-copper-interconnect-for-ics | title=Ibm's Development of Copper Interconnect for Integrated Circuit }}</ref>

In 2014, Applied Materials proposed the use of cobalt in interconnects at the 22nm node, used for encapsulating copper interconnects in cobalt to prevent electromigration, replacing tantalum nitride since it needs to be thicker than cobalt in this application.<ref name="auto7"/><ref>{{cite web | url=https://www.eetimes.com/cobalt-encapsulation-extends-copper-to-10nm/ | title=Cobalt Encapsulation Extends Copper to 10nm | date=13 May 2014 }}</ref>