Editing PDP-8 (section)

===OPR (OPeRate)===
Many operations are achieved using OPR, including most of the conditionals. OPR does not address a memory location; conditional execution is achieved by conditionally skipping the following instruction, which is typically a JMP.

The OPR instruction was said to be "microcoded." This did not mean what the word means today (that a lower-level program fetched and interpreted the OPR instruction), but meant that each bit of the instruction word specifies a certain action, and the programmer could achieve several actions in a single instruction cycle by setting multiple bits. In use, a programmer can write several instruction mnemonics alongside one another, and the assembler combines them with [[logical disjunction|OR]] to devise the actual instruction word. Many I/O devices support "microcoded" IOT instructions.

Microcoded actions take place in a well-defined sequence designed to maximize the utility of many combinations.

The OPR instructions come in Groups. Bits 3, 8 and 11 identify the Group of an OPR instruction, so it is impossible to combine the microcoded actions from different groups.

One action (and corresponding bit) which is the same in all groups is bit 4, CLA.  If set, the accumulator is cleared.

====Group 1====
<pre>
        00 01 02 03 04 05 06 07 08 09 10 11
        ___________________________________
       | 1| 1| 1| 0|  |  |  |  |  |  |  |  |
       |__|__|__|__|__|__|__|__|__|__|__|__|
                   |CLA   CMA   RAR   BSW
                       CLL   CML   RAL   IAC

    Execution order  1  1  2  2  4  4  4  3
</pre>
:7200 – CLA – Clear Accumulator
:7100 – CLL – Clear the L Bit
:7040 – CMA – Ones Complement Accumulator
:7020 – CML – Complement L Bit
:7001 – IAC – Increment <L,AC>
:7010 – RAR – Rotate <L,AC> Right
:7004 – RAL – Rotate <L,AC> Left
:7012 – RTR – Rotate <L,AC> Right Twice
:7006 – RTL – Rotate <L,AC> Left Twice
:7002 – BSW – Byte Swap 6-bit "bytes" (PDP 8/e and up)

In most cases, the operations are sequenced so that they can be combined in the most useful ways. For example, combining CLA (CLear Accumulator), CLL (CLear Link), and IAC (Increment ACcumulator) first clears the AC and Link, then increments the accumulator, leaving it set to 1. Adding RAL to the mix (so CLA CLL IAC RAL) causes the accumulator to be cleared, incremented, then rotated left, leaving it set to 2. In this way, small integer constants were placed in the accumulator with a single instruction.

The combination CMA IAC, which the assembler lets you abbreviate as CIA, produces the arithmetic inverse of AC: the twos-complement negation. Since there is no subtraction instruction, only the twos-complement add (TAD), computing the difference of two operands, requires first negating the subtrahend.

A Group 1 OPR instruction that has none of the microprogrammed bits set performs no action. The programmer can write [[NOP (code)|NOP]] (No Operation) to assemble such an instruction.

====Group 2, Or Group====
<pre>
         00 01 02 03 04 05 06 07 08 09 10 11
        ___________________________________
       | 1| 1| 1| 1|  |  |  |  | 0|  |  | 0|
       |__|__|__|__|__|__|__|__|__|__|__|__|
                   |CLA   SZA      OSR
                       SMA   SNL      HLT

                     2  1  1  1     3  3
</pre>
:7600 – CLA – Clear AC
:7500 – SMA – Skip on AC < 0 (or group)
:7440 – SZA – Skip on AC = 0 (or group)
:7420 – SNL – Skip on L ≠ 0 (or group)
:7404 – OSR – [[bitwise operation|logically 'or']] front-panel switches with AC
:7402 – HLT – Halt

Three of the bits (CLA, OSR, HLT) perform actions if set.  Another three bits (SMA, SZA, SNL) encode skip conditions; a skip is performed if any of the specified conditions are true.  For example, "SMA SZA", opcode 7540, skips if AC ≤ 0.

A Group 2 OPR instruction that has none of the microprogrammed bits set is another No-Op instruction.

====Group 2, And Group====
<pre>
         00 01 02 03 04 05 06 07 08 09 10 11
        ___________________________________
       | 1| 1| 1| 1|  |  |  |  | 1|  |  | 0|
       |__|__|__|__|__|__|__|__|__|__|__|__|
                   |CLA   SNA      OSR
                       SPA   SZL      HLT

                     2  1  1  1     3  2
</pre>
:7410 – SKP – Skip Unconditionally
:7610 – CLA – Clear AC
:7510 – SPA – Skip on AC ≥ 0 (and group)
:7450 – SNA – Skip on AC ≠ 0 (and group)
:7430 – SZL – Skip on L = 0 (and group)

When bit 8 is set, the Group 2 skip condition is inverted; the skip is ''not'' performed if any of the or group conditions are true.  By [[De Morgan's laws]], this means that the skip ''is'' performed if all of the specified inverted conditions are true.  For example, "SPA SNA", opcode 7550, skips if AC > 0. If none of bits 5–7 are set, then the skip is unconditional.

The actions (CLA, OSR, HLT) are not affected by bit 8.

====Group 3====
Unused bit combinations of OPR are defined as a third Group of microprogrammed actions mostly affecting the MQ (Multiplier/Quotient) register.  The MQ register and the extended arithmetic element (EAE) instructions are optional and only exist when EAE option was purchased.<ref>{{cite book |title=Small Computer Handbook 1967–1968 |date=1968 |publisher=Digital Equipment Corporation |pages=130–136}}</ref>
<pre>
        00 01 02 03 04 05 06 07 08 09 10 11
        ___________________________________
       | 1| 1| 1| 1|  |  |  |  |  |  |  | 1|
       |__|__|__|__|__|__|__|__|__|__|__|__|
                   |CLA   SCA   \_    _/
                   |   MQA   MQL  CODE

                     1* 2  2  2     3
</pre>
:7601 – CLA – Clear AC
:7501 – MQA – Multiplier Quotient with AC (logical or MQ into AC)
:7441 – SCA – Step counter load into AC
:7421 – MQL – Multiplier Quotient Load (Transfer AC to MQ, clear AC)
:7621 – CAM – CLA + MQL clears both AC and MQ.

Typically CLA and MQA were combined to transfer MQ into AC. Another useful combination is MQA and MQL, to exchange the two registers.

Three bits specified a multiply/divide instruction to perform:
:7401 – No operation
:7403 – SCL – Step Counter Load (immediate word follows, PDP-8/I and up)
:7405 – MUY – Multiply
:7407 – DVI – Divide
:7411 – NMI – Normalize
:7413 – SHL – Shift left (immediate word follows)
:7415 – ASR – Arithmetic shift right
:7417 – LSR – Logical shift right