Editing PDP-10 (section)

==Instruction set architecture==
From the first PDP-6s to the KL-10 and KS-10, the user-mode [[instruction set architecture]] is largely the same. This section covers that architecture.  The only major change to the architecture is the addition of multi-section extended addressing in the KL-10; extended addressing, which changes the process of generating the effective address of an instruction, is briefly discussed at the end. Generally, the system has 36-bit words and instructions, and 18-bit addresses.

=== Registers ===
{| class="infobox" style="font-size:88%;width:36em;"
|-
|+ DEC PDP-10 registers
|-
|
{| style="font-size:88%;"
|- 
| style="width:10px; text-align:center;"| <sup>0</sup><sub>0</sub>
| style="width:120px; text-align:center;"| . . .
| style="width:10px; text-align:center;"| <sup>1</sup><sub>7</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>8</sub>
| style="width:120px; text-align:center;"| . . .
| style="width:10px; text-align:center;"| <sup>3</sup><sub>5</sub>
| style="width:auto; background:white; color:black" | ''(bit position)''
|- 
|colspan="7" | '''General registers'''
|- style="background:silver;color:black"
| style="text-align:center" colspan="6"| <div style="display:inline-block; width:12px">&nbsp;</div> AC0
| style="background:white; color:black;"| '''R'''egister 0
|- style="background:silver;color:black"
| style="text-align:right" colspan="3"| &nbsp;
| style="text-align:left;" colspan="3"| AC1
| style="background:white; color:black;"| '''R'''egister 1
|- style="background:silver;color:black"
| style="text-align:right" colspan="3"| &nbsp;
| style="text-align:left;" colspan="3"| AC2
| style="background:white; color:black;"| '''R'''egister 2
|- style="background:silver;color:black"
| style="text-align:right" colspan="3"| &nbsp;
| style="text-align:left;" colspan="3"| AC3
| style="background:white; color:black;"| '''R'''egister 3
|- style="background:silver;color:black"
| style="text-align:right" colspan="3"| &nbsp;
| style="text-align:left;" colspan="3"| AC4
| style="background:white; color:black;"| '''R'''egister 4
|- style="background:silver;color:black"
| style="text-align:right" colspan="3"| &nbsp;
| style="text-align:left;" colspan="3"| AC5
| style="background:white; color:black;"| '''R'''egister 5
|- style="background:silver;color:black"
| style="text-align:right" colspan="3"| &nbsp;
| style="text-align:left;" colspan="3"| AC6
| style="background:white; color:black;"| '''R'''egister 6
|- style="background:silver;color:black"
| style="text-align:right" colspan="3"| &nbsp;
| style="text-align:left;" colspan="3"| AC7
| style="background:white; color:black;"| '''R'''egister 7
|- style="background:silver;color:black"
| style="text-align:right" colspan="3"| &nbsp;
| style="text-align:left;" colspan="3"| AC10
| style="background:white; color:black;"| '''R'''egister 8
|- style="background:silver;color:black"
| style="text-align:right" colspan="3"| &nbsp;
| style="text-align:left;" colspan="3"| AC11
| style="background:white; color:black;"| '''R'''egister 9
|- style="background:silver;color:black"
| style="text-align:right" colspan="3"| &nbsp;
| style="text-align:left;" colspan="3"| AC12
| style="background:white; color:black;"| '''R'''egister 10
|- style="background:silver;color:black"
| style="text-align:right" colspan="3"| &nbsp;
| style="text-align:left;" colspan="3"| AC13
| style="background:white; color:black;"| '''R'''egister 11
|- style="background:silver;color:black"
| style="text-align:right" colspan="3"| &nbsp;
| style="text-align:left;" colspan="3"| AC14
| style="background:white; color:black;"| '''R'''egister 12
|- style="background:silver;color:black"
| style="text-align:right" colspan="3"| &nbsp;
| style="text-align:left;" colspan="3"| AC15
| style="background:white; color:black;"| '''R'''egister 13
|- style="background:silver;color:black"
| style="text-align:right" colspan="3"| &nbsp;
| style="text-align:left;" colspan="3"| AC16
| style="background:white; color:black;"| '''R'''egister 14
|- style="background:silver;color:black"
| style="text-align:right" colspan="3"| &nbsp;
| style="text-align:left;" colspan="3"| AC17
| style="background:white; color:black;"| '''R'''egister 15
|- 
|colspan="7" | '''Program counter and status flags'''
|- style="background:silver;color:black"
| style="text-align:left;" colspan="2"| Program Flags
| style="text-align:right;"| '''00000'''
| style="text-align:center" colspan="3"| PC
| style="background:white; color:black;"| '''P'''rogram '''C'''ounter
|} 
Note that the bit numbering order is different from some other DEC processors, and many newer processors.
|}

There are 16 general-purpose, 36-bit registers.  The right half of these registers (other than register 0) may be used for indexing. A few instructions operate on pairs of registers. The "PC Word" register is split in half; the right 18 bits contains the [[program counter]] and the left 13 bits contains the [[status register|processor status flag]]s, with five zeros between the two sections. The condition register bits, which record the results of arithmetic operations (''e.g.'' overflow), can be accessed by only a few instructions.

In the original KA-10 systems, these registers are simply the first 16 words of [[main memory]]. The "fast registers" hardware option implements them as registers in the CPU, still addressable as the first 16 words of memory. Some software takes advantage of this by using the registers as an [[CPU cache|instruction cache]] by loading code into the registers and then jumping to the appropriate address; this is used, for example, in [[Maclisp]] to implement one version of the [[Garbage collection (computer science)|garbage collector]].<ref>{{cite web |url=http://www.paulgraham.com/thist.html|title=History of T|first=Olin|last=Shivers|access-date=October 25, 2019|quote=Maclisp on the -10 had used a mark&sweep GC (one version of which famously "ran in the register set," though that is another story)}}</ref> Later models all have registers in the CPU.

=== Supervisor mode ===
There are two operational modes, supervisor and user mode. Besides the difference in memory referencing described above, supervisor-mode programs can execute input/output operations.

Communication from user-mode to supervisor-mode is done through Unimplemented User Operations (UUOs): instructions which are not defined by the hardware, and are trapped by the supervisor. This mechanism is also used to emulate operations which may not have hardware implementations in cheaper models.

=== Data types ===
The major datatypes which are directly supported by the architecture are [[two's complement]] 36-bit integer arithmetic (including bitwise operations), 36-bit floating-point, and halfwords. Extended, 72-bit, floating point is supported through special instructions designed to be used in multi-instruction sequences. Byte pointers are supported by special instructions. A word structured as a "count" half and a "pointer" half facilitates the use of bounded regions of memory, notably [[Stack-based memory allocation|stacks]].

=== Instructions ===
{| class="infobox" style="font-size:88%;width:36em;"
|-
|+ DEC PDP-10 instruction formats
|-
|
{| style="font-size:88%;"
|- 
| style="width:10px; text-align:center;"| <sup>0</sup><sub>0</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>1</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>2</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>3</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>4</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>5</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>6</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>7</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>8</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>9</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>0</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>1</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>2</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>3</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>4</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>5</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>6</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>7</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>8</sub>
| style="width:60px; text-align:center;"| . . .
| style="width:10px; text-align:center;"| <sup>3</sup><sub>5</sub>
| style="width:auto; background:white; color:black" | ''(bit position)''
|- 
|colspan="20" | '''General instructions'''
|- style="background:silver;color:black"
| style="text-align:center" colspan="9"| <div style="display:inline-block; width:12px">&nbsp;</div> Opcode
| style="text-align:center" colspan="4"| <div style="display:inline-block; width:6px">&nbsp;</div> Acc #
| style="text-align:center" colspan="1"| <div style="display:inline-block; width:0px">&nbsp;</div> I
| style="text-align:center" colspan="4"| <div style="display:inline-block; width:0px">&nbsp;</div> Index #
| style="text-align:center" colspan="17"| <div style="display:inline-block; width:12px">&nbsp;</div> Memory address
|- 
|colspan="12" | '''I/O instructions'''
|- style="background:silver;color:black"
| style="text-align:center" colspan="3"| <div style="display:inline-block; width:8px">&nbsp;</div> 7
| style="text-align:center" colspan="7"| <div style="display:inline-block; width:12px">&nbsp;</div> Device #
| style="text-align:center" colspan="3"| Opcode
| style="text-align:center" colspan="1"| <div style="display:inline-block; width:0px">&nbsp;</div> I
| style="text-align:center" colspan="4"| <div style="display:inline-block; width:0px">&nbsp;</div> Index #
| style="text-align:center" colspan="17"| <div style="display:inline-block; width:12px">&nbsp;</div> Memory address
|} 
|}
Instructions are stored in 36-bit words. There are two formats, general instructions and [[input/output]] instructions.{{sfn|Programming|1970|p=13}}

In general instructions, the leftmost 9 bits, 0 to 8, contain an instruction [[opcode]]. Many of the possible 512 codes are not defined in the base model machines and are reserved for expansion like the addition of a hardware [[floating point unit]]. Following the opcode in bits 9 to 12 is the number of a register which will be used for the instruction. The input/output instructions all start with bits 0 through 2 being set to 1 (decimal value 7), bits 3 through 9 containing a device number, and 10 through 12 the instruction opcode.{{sfn|Programming|1970|p=13}}

In both formats, bits 13 through 35 are used to form the "effective address", E. Bits 18 through 35 contain a numerical constant address, Y. This address may be modified by adding the 18-bit value in a register, X, the register number indicated in bits 14 to 17. If these are set to zero, no indexing is used, meaning register 0 cannot be used for indexing. Bit 13, I, indicates indirection, meaning the ultimate effective address used by the instruction is not E, but the address stored in memory location E. When using indirection, the data in word E is interpreted in the same way as the layout of the instruction; bits 0 to 12 are ignored, and 13 through 35 form I, X and Y as above.

Instruction execution begins by calculating E. It adds the contents of the given register X (if not 0) to the offset Y; then, if the indirect bit is 1, the value at E is fetched and the effective address calculation is repeated. If I is 1 in the stored value at E in memory, the system will then indirect through that address as well, possibly following many such steps.{{sfn|Programming|1970|p=13}} This process continues until an indirect word with a zero indirect bit is reached. Indirection of this sort was a common feature of processor designs of this era.

In supervisor mode, addresses correspond directly to physical memory. In user mode, addresses are translated to physical memory. Earlier models give a user process a "high" and a "low" memory: addresses with a 0 top bit use one base register and those with a 1 use another. Each segment is contiguous.  Later architectures have paged memory access, allowing non-contiguous address spaces. The CPU's general-purpose registers can also be addressed as memory locations 0–15.

====General instructions====
There are three main classes of general instructions: arithmetic, logical, and move; conditional jump; conditional skip (which may have side effects). There are also several smaller classes.

The arithmetic, logical, and move operations include variants which operate immediate-to-register, memory-to-register, register-to-memory, register-and-memory-to-both or memory-to-memory. Since registers may be addressed as part of memory, register-to-register operations are also defined. (Not all variants are useful, though they are well-defined.) For example, the ADD operation has as variants ADDI (add an 18-bit ''I''mmediate constant to a register), ADDM (add register contents to a ''M''emory location), ADDB (add to ''B''oth, that is, add register contents to memory and also put the result in the register). A more elaborate example is HLROM (''H''alf ''L''eft to ''R''ight, ''O''nes to ''M''emory), which takes the Left half of the register contents, places them in the Right half of the memory location, and replaces the left half of the memory location with Ones. Halfword instructions are also used for linked lists: HLRZ is the Lisp CAR operator; HRRZ is CDR.

The conditional jump operations examine register contents and jump to a given location depending on the result of the comparison. The mnemonics for these instructions all start with JUMP, JUMPA meaning "jump always" and JUMP meaning "jump never" – as a consequence of the symmetric design of the instruction set, it contains several no-ops such as JUMP. For example, JUMPN A,LOC jumps to the address LOC if the contents of register A is non-zero. There are also conditional jumps based on the processor's condition register using the JRST instruction. On the KA10 and KI10, JRST is faster than JUMPA, so the standard unconditional jump is JRST.

The conditional skip operations compare register and memory contents and skip the next instruction (which is often an unconditional jump) depending on the result of the comparison. A simple example is CAMN A,LOC which compares the contents of register A with the contents of location LOC and skips the next instruction if they are not equal.  A more elaborate example is TLCE A,LOC (read "Test Left Complement, skip if Equal"), which using the contents of LOC as a mask, selects the corresponding bits in the left half of register A. If all those bits are ''E''qual to zero, skip the next instruction; and in any case, replace those bits by their Boolean complement.

Some smaller instruction classes include the shift/rotate instructions and the procedure call instructions. Particularly notable are the stack instructions PUSH and POP, and the corresponding stack call instructions PUSHJ and POPJ. The byte instructions use a special format of indirect word to extract and store arbitrary-sized bit fields, possibly advancing a pointer to the next unit.{{efn|cf. {{section link|Byte addressing|Hybrid systems}}}}

====Input/output instructions====
The PDP-10 does not use [[Memory-mapped I/O and port-mapped I/O|memory-mapped devices]], in contrast to the [[PDP-11]] and later DEC machines. A separate set of instructions is used to move data to and from devices defined by a device number in the instruction. Bits 3 to 9 contain the device number, with the 7 bits allowing a total of 128 devices. Instructions allow for the movement of data to and from devices in word-at-a-time (DATAO and DATAI) or block-at-a-time (BLKO, BLKI).{{sfn|Programming|1970|pp=87-88}}

In block mode, the value pointed to by E is a word in memory that is split in two, the right 18 bits indicate a starting address in memory where the data is located (or written into) and the left 18 bits are a counter. The block instructions increment both values every time they are called, thereby increasing the counter as well as moving to the next location in memory. It then performs a DATAO or DATAI. Finally, it checks the counter side of the value at E, if it is non-zero, it skips the next instruction. If it is zero, it performs the next instruction, normally a JUMP back to the top of the loop.{{sfn|Programming|1970|p=88}} The BLK instructions are effectively small programs that loop over a DATA and increment instructions, but by having this implemented in the processor itself, it avoids the need to repeatedly read the series of instructions from main memory and thus performs the loop much more rapidly.{{sfn|Programming|1970|p=89}}

The final set of I/O instructions are used to write and read condition codes on the device, CONO and CONI.{{sfn|Programming|1970|p=86}} Additionally, CONSZ will perform a CONI, bitmask the retrieved data against the value in E, and then skip the next instruction if it is zero, used in a fashion similar to the BLK commands. Only the right 18 bits are tested in CONSZ.{{sfn|Programming|1970|p=87}}

===Interrupt handling===
A second use of the CONO instruction is to set the device's priority level for [[interrupt]] handling. There are three bits in the CONO instruction, 33 through 35, allowing the device to be set to level 0 through 7. Level 1 is the highest, meaning that if two devices raise an interrupt at the same time, the lowest-numbered device will begin processing. Level 0 means "no interrupts", so a device set to level 0 will not stop the processor even if it does raise an interrupt.{{sfn|Programming|1970|p=92}}

Each device channel has two memory locations associated with it, one at 40+2N and the other at 41+2N, where N is the channel number. Thus, channel 1 uses locations 42 and 43. When the interrupt is received and accepted, meaning no higher-priority interrupt is already running, the system stops at the next memory read part of the [[instruction cycle]] and instead begins processing at the address stored in the first of those two locations. It is up to the [[interrupt handler]] to turn off the interrupt level when it is complete, which it can do by running a CONO, DATA or BLK instruction.{{sfn|Programming|1970|p=92}} As a special case, if the instruction is BLKI or BLKO, and the incremented count is not zero, the interrupt is dismissed immediately, otherwise the second instruction is executed to process the interrupt. This provided a low-cost medium performance version of direct memory access.

Two of the device numbers are set aside for special purposes. Device 0 is the computer's front-panel console; reading that device retrieves the settings of the panel switches while writing lights up the status lamps. Device 4 is the "priority interrupt", which can be read using CONI to gain additional information about an interrupt that has occurred.{{sfn|Programming|1970|p=94}}

===Extended addressing===
In processors supporting extended addressing, the address space is divided into "sections".  An 18-bit address is a "local address", containing an offset within a section, and a "global address" is 30 bits, divided into a 12-bit section number at the bottom of the left 18 bits and an 18-bit offset within that section in the right 18 bits.  A register can contain either a "local index", with an 18-bit unsigned displacement or local address in the right 18 bits, or a "global index", with a 30-bit unsigned displacement or global address in the right 30 bits.  An indirect word can either be a "local indirect word", with its uppermost bit set, the next 12 bits reserved, and the remaining bits being an indirect bit, a 4-bit register code, and an 18-bit displacement, or a "global indirect word", with its uppermost bit clear, the next bit being an indirect bit, the next 4 bits being a register code, and the remaining 30 bits being a displacement.<ref name=referencemanual>{{cite web |title=DECsystem-10/DECSYSTEM-20 Processor Reference Manual|id=AA-H391A-TK, AD-H391A-T1|url=http://www.36bit.org/dec/manual/ad-h391a-t1.pdf |publisher=Digital Equipment Corporation |date=June 1982 |access-date=November 14, 2015 |url-status=dead |archive-url=https://web.archive.org/web/20151011152807/http://www.36bit.org/dec/manual/ad-h391a-t1.pdf |archive-date=October 11, 2015}}</ref>{{rp|1-26&ndash;1-30}}

The process of calculating the effective address generates a 12-bit section number and an 18-bit offset within that segment.<ref name="referencemanual"/>{{rp|1-26&ndash;1-30}}