Editing Flash memory (section)

===NOR flash===
[[File:NOR flash layout.svg|thumb|350px|right| NOR flash memory wiring and structure on silicon]]

In NOR flash, each cell has one end connected directly to ground, and the other end connected directly to a bit line. This arrangement is called "NOR flash" because it acts like a [[NOR gate|NOR&nbsp;gate;]]  when one of the word lines (connected to the cell's CG) is brought high, the corresponding storage transistor acts to pull the output bit line low. NOR flash continues to be the technology of choice for embedded applications requiring a discrete non-volatile memory device.{{citation needed|date=May 2022}} The low read latencies characteristic of NOR&nbsp;devices allow for both direct code execution and data storage in a single memory product.<ref name="eetimes-20110502">{{Cite news |last=Zitlaw |first=Cliff |date=2 May 2011 |title=The Future of NOR Flash Memory |work=Memory Designline |publisher=UBM Media |url=https://www.eetimes.com/the-future-of-nor-flash-memory/ |url-status=live |access-date=3 May 2011 |archive-url=https://web.archive.org/web/20230601001439/https://www.eetimes.com/the-future-of-nor-flash-memory/ |archive-date=1 June 2023 }}</ref>

====Programming====
[[Image:Flash-Programming.svg|thumb|left|Programming a NOR memory cell (setting it to logical 0), via hot-electron injection]]
[[File:Flash erase.svg|thumb|right|Erasing a NOR memory cell (setting it to logical 1), via quantum tunneling]]

A single-level NOR flash cell in its default state is logically equivalent to a binary "1" value, because current will flow through the channel under application of an appropriate voltage to the control gate, so that the bitline voltage is pulled down. A NOR&nbsp;flash cell can be programmed, or set to a binary "0" value, by the following procedure:

* an elevated on-voltage (typically >5&nbsp;V) is applied to the CG
* the channel is now turned on, so electrons can flow from the source to the drain (assuming an NMOS&nbsp;transistor)
* the source-drain current is sufficiently high to cause some high energy electrons to jump through the insulating layer onto the FG, via a process called [[hot carrier injection|hot-electron injection]].

====Erasing====
To erase a NOR flash cell (resetting it to the "1" state), a large voltage ''of the opposite polarity'' is applied between the CG and source terminal, pulling the electrons off the FG through [[Fowler–Nordheim tunneling]] (FN tunneling).<ref>{{cite book | url=https://books.google.com/books?id=44mbEAAAQBAJ&dq=nor+flash+erase&pg=PA55 | isbn=978-3-030-79827-7 | title=Springer Handbook of Semiconductor Devices | date=10 November 2022 | publisher=Springer }}</ref> This is known as Negative gate source source erase. Newer NOR memories can erase using negative gate channel erase, which biases the wordline on a NOR memory cell block and the P-well of the memory cell block to allow FN tunneling to be carried out, erasing the cell block. Older memories used source erase, in which a high voltage was applied to the source and then electrons from the FG were moved to the source.<ref>{{cite book | url=https://books.google.com/books?id=2E0r6BRo2VkC&dq=nor+flash+erase&pg=PA212 | isbn=978-90-481-9216-8 | title=CMOS Processors and Memories | date=9 August 2010 | publisher=Springer }}</ref><ref>{{cite journal | url=https://ieeexplore.ieee.org/document/1035946 | title=  High-voltage transistor scaling circuit techniques for high-density negative-gate channel-erasing NOR flash memories| date= 2002| doi=10.1109/JSSC.2002.803045 | last1= Tanzawa| first1= T.| last2= Takano| first2= Y.| last3= Watanabe| first3= K.| last4= Atsumi| first4= S.| journal= IEEE Journal of Solid-State Circuits| volume= 37| issue= 10| pages= 1318–1325| bibcode= 2002IJSSC..37.1318T}}</ref> Modern NOR&nbsp;flash memory chips are divided into erase segments (often called blocks or sectors). The erase operation can be performed only on a block-wise basis; all the cells in an erase segment must be erased together.<ref>{{cite book | url=https://books.google.com/books?id=abfBAAAAQBAJ&dq=nor+erase+block&pg=PA41 | isbn=978-94-007-6082-0 | title=Flash Memories: Economic Principles of Performance, Cost and Reliability Optimization | date=12 September 2013 | publisher=Springer }}</ref> Programming of NOR cells, however, generally can be performed one byte or word at a time.

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[[File:Nand flash structure.svg|thumb|350px|right|NAND flash memory wiring and structure on silicon]]