Editing Field-programmable gate array (section)

=== Clocking ===
Most of the logic inside of an FPGA is [[synchronous circuit]]ry that requires a [[clock signal]]. FPGAs contain dedicated global and regional routing networks for clock and reset, typically implemented as an [[H tree]], so they can be delivered with minimal [[Clock skew|skew]]. FPGAs may contain analog [[phase-locked loop]] or [[delay-locked loop]] components to synthesize new [[clock frequencies]] and manage [[jitter]]. Complex designs can use multiple clocks with different frequency and phase relationships, each forming separate [[clock domain]]s. These clock signals can be generated locally by an oscillator or they can be recovered from a [[data stream]]. Care must be taken when building [[clock domain crossing]] circuitry to avoid [[Metastability (electronics)|metastability]]. Some FPGAs contain [[dual port RAM]] blocks that are capable of working with different clocks, aiding in the construction of building [[FIFO (computing and electronics)|FIFOs]] and dual port buffers that bridge clock domains.