Editing Direct memory access (section)

=== PCI ===
A [[Peripheral Component Interconnect|PCI]] architecture has no central DMA controller, unlike ISA. Instead, A PCI device can request control of the bus ("become the [[bus master]]") and request to read from and write to system memory. More precisely, a PCI component requests bus ownership from the PCI bus controller (usually PCI host bridge, and PCI to PCI bridge<ref>{{Cite web|title=Bus Specifics - Writing Device Drivers for Oracle® Solaris 11.3|url=https://docs.oracle.com/cd/E53394_01/html/E54850/hwovr-25520.html|access-date=2020-12-18|website=docs.oracle.com}}</ref>), which will [[Arbiter (electronics)|arbitrate]] if several devices request bus ownership simultaneously, since there can only be one bus master at one time. When the component is granted ownership, it will issue normal read and write commands on the PCI bus, which will be claimed by the PCI bus controller.

As an example, on an [[Intel Core]]-based PC, the southbridge will forward the transactions to the [[memory controller]] (which is [[Integrated circuit design|integrated]] on the CPU die) using [[Direct Media Interface|DMI]], which will in turn convert them to DDR operations and send them out on the memory bus. As a result, there are quite a number of steps involved in a PCI DMA transfer; however, that poses little problem, since the PCI device or PCI bus itself are an order of magnitude slower than the rest of the components (see [[list of device bandwidths]]).

A modern x86 CPU may use more than 4 GB of memory, either utilizing the native 64-bit mode of [[x86-64]] CPU, or the [[Physical Address Extension]] (PAE), a 36-bit addressing mode. In such a case, a device using DMA with a 32-bit address bus is unable to address memory above the 4 GB line. The new [[Double Address Cycle]] (DAC) mechanism, if implemented on both the PCI bus and the device itself,<ref>{{cite web|url=http://www.microsoft.com/whdc/system/platform/server/PAE/PAEdrv.mspx#E2D|title=Physical Address Extension&nbsp;— PAE Memory and Windows|publisher=Microsoft Windows Hardware Development Central|year=2005|access-date=2008-04-07}}</ref> enables 64-bit DMA addressing. Otherwise, the operating system would need to work around the problem by either using costly [[double buffering (DMA)|double buffer]]s (DOS/Windows nomenclature) also known as [[bounce buffer]]s ([[FreeBSD]]/Linux), or it could use an [[IOMMU]] to provide address translation services if one is present.