Editing Deflate (section)

=== Hardware decoders ===
* [https://web.archive.org/web/20171010000403/http://www.bitsim.com/en/our-design-model/#Blocks Serial Inflate GPU] from BitSim. Hardware implementation of Inflate. Part of the Bitsim Accelerated Display Graphics Engine (BADGE) controller offering for embedded systems.
* [https://github.com/tomtor/HDL-deflate HDL-Deflate] GPL FPGA implementation.
* [https://www.cast-inc.com/compression/gzip-lossless-data-compression/zipaccel-d/ ZipAccel-D] from [https://www.cast-inc.com/ CAST Inc]. This is a Silicon IP core supporting decompression of Deflate, [[Zlib]] and [[Gzip]] files. The ZipAccel-D IP core that can be implemented in [[Application-specific integrated circuit|ASIC]] or [[Field-programmable gate array|FPGAs]]. The company offers compression/decompression accelerator board reference designs for Intel FPGA ([https://www.cast-inc.com/compression/gzip-lossless-data-compression/gzip-rd-int/ ZipAccel-RD-INT]) and Xilinx FPGAs ([https://www.cast-inc.com/compression/gzip-lossless-data-compression/gzip-rd-xil/ ZipAccel-RD-XIL]).
* [[IBM z15 (microprocessor)|IBM z15]] CPUs incorporate an improved version of the Nest Accelerator Unit (NXU) hardware acceleration from the zEDC Express [[input/output]] (I/O) expansion cards used in z14 systems for hardware Deflate compression and decompression as specified by RFC1951.<ref name="z15_announce"/><ref name="z15_techmanual"/>
* Starting with the [[POWER9]] architecture, IBM added hardware support for compressing and decompressing Deflate (as specified by RFC 1951) to the formerly crypto-centric Nest accelerator (NX) core introduced with [[POWER7]]+. This support is available to programs running with [[IBM AIX|AIX]] 7.2 Technology Level 4 Expansion Pack or AIX 7.2 Technology Level 5 Service Pack 2 through the zlibNX library.<ref name="zlibnx"/><ref name="power7_accel"/>