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== Further reading == * [[Eby Friedman|Eby G. Friedman]] (Ed.), ''Clock Distribution Networks in VLSI Circuits and Systems'', {{ISBN|0-7803-1058-6}}, IEEE Press. 1995. * [[Eby Friedman|Eby G. Friedman]], {{doi-inline|10.1109/5.929649|"Clock Distribution Networks in Synchronous Digital Integrated Circuits"}}, ''Proceedings of the IEEE'', Vol. 89, No. 5, pp. 665β692, May 2001. * [http://archive.sigda.org/ispd/contests/10/ispd10cns.html "ISPD 2010 High Performance Clock Network Synthesis Contest"], International Symposium on Physical Design, Intel, IBM, 2010. * D.-J. Lee, [http://www.eecs.umich.edu/~imarkov/pubs/diss/DJdiss.pdf "High-performance and Low-power Clock Network Synthesis in the Presence of Variation"], Ph.D. dissertation, University of Michigan, 2011. * [[Igor L. Markov|I. L. Markov]], D.-J. Lee, [http://www.eecs.umich.edu/~imarkov/pubs/conf/iccad11-tuto.pdf "Algorithmic Tuning of Clock Trees and Derived Non-Tree Structures"], in Proc. Int'l. Conf. Comp.-Aided Design (ICCAD), 2011. * V. G. Oklobdzija, V. M. Stojanovic, D. M. Markovic, and N. M. Nedovic, ''Digital System Clocking: High-Performance and Low-Power Aspects'', {{ISBN|0-471-27447-X}}, IEEE Press/Wiley-Interscience, 2003. * Mitch Dale, [https://web.archive.org/web/20131224102708/http://chipdesignmag.com/display.php?articleId=915 "The power of RTL Clock-gating"], ''Electronic Systems Design Engineering Incorporating Chip Design'', January 20, 2007. ---- Adapted from [http://www.ece.rochester.edu/users/friedman/ Eby Friedman] {{Webarchive|url=https://web.archive.org/web/20140812225312/http://www.ece.rochester.edu/users/friedman/ |date=2014-08-12 }}'s column in the ACM [http://www.sigda.org SIGDA] [https://web.archive.org/web/20070208034716/http://www.sigda.org/newsletter/index.html e-newsletter] by [http://www.eecs.umich.edu/~imarkov/ Igor Markov]<br /> Original text is available at https://web.archive.org/web/20100711135550/http://www.sigda.org/newsletter/2005/eNews_051201.html [[Category:Clock signal| ]] [[Category:Synchronization]]
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