Editing Athlon (section)

====''Barton'' / ''Thorton''====
[[File:KL AMD Athlon XP Barton.jpg|thumb|150px|Athlon XP "Barton" 2500+]]

Fifth-generation Athlon ''Barton''-core processors were released in early 2003. While not operating at higher clock rates than ''Thoroughbred''-core processors, they featured an increased L2 cache, and later models had an increased 200&nbsp;MHz (400&nbsp;MT/s) front side bus.<ref name=AceBarton>{{citation |author=De Gelas, Johan |url=http://www.aceshardware.com/read.jsp?id=50000364 |archive-url=https://web.archive.org/web/20030324002539/http://www.aceshardware.com/read.jsp?id=50000364|title=Barton: 512 KB Athlon XP Reviewed |publisher=Ace's Hardware |date=February 10, 2003 |archive-date=March 24, 2003 |access-date=January 6, 2012}}.</ref> The ''Thorton'' core, a blend of ''Thoroughbred'' and ''Barton'', was a later variant of the ''Barton'' with half of the L2 cache disabled.<ref>{{Cite web |url=http://www.cpu-world.com/Cores/Thorton.html |title=AMD Thorton core}}</ref> The ''Barton'' was used to officially introduce a higher 400&nbsp;MT/s bus clock for the Socket&nbsp;A platform, which was used to gain some ''Barton'' models more efficiency.<ref name=AceBarton /> By this point with the ''Barton'', the four-year-old Athlon EV6&nbsp;bus architecture had scaled to its limit and required a redesign to exceed the performance of newer Intel processors.<ref name=AceBarton /> By 2003, the [[Pentium&nbsp;4]] had become more than competitive with AMD's processors,<ref name=BartonAnand>{{citation |author=Lal Shimpi, Anand |url=http://www.anandtech.com/show/1066|title=AMD's Athlon XP 3000+: Barton cuts it close |publisher=AnandTech |date=February 10, 2003 |access-date=January 6, 2012}}.</ref> and ''Barton'' only saw a small performance increase over the ''Thoroughbred-B'' it derived from,<ref name=AceBarton /> insufficient to outperform the Pentium&nbsp;4.<ref name=BartonAnand /> The K7-derived Athlons such as ''Barton'' were replaced in September 2003 by the [[AMD K8|Athlon&nbsp;64]] family, which featured an [[Memory controller|on-chip memory controller]] and a new [[HyperTransport]] bus.<ref name="Wasson for Tech Report again I think: 2020">{{cite web |url=https://techreport.com/review/6070/amds-athlon-64-3400-processor/|title=AMD's Athlon 64 3400+ process|author=Scott Wasson |date=January 6, 2020|publisher=The Tech Report |access-date=August 4, 2020}}</ref>

Notably, the 2500+ Barton with 11× multiplier was effectively identical to the 3200+ part other than the FSB speed it was binned for, meaning that seamless overclocking was possible more often than not. Early Thortons could be restored to the full Barton specification with the enabling of the other half of the L2 cache from a slight CPU surface modification, but the result was not always reliable.

;Specifications:
''Barton (130&nbsp;nm)''
* L1-cache: 64 + 64&nbsp;KB (data + instructions)
* L2-cache: 512&nbsp;KB, full speed
* [[MMX (instruction set)|MMX]], [[3DNow!]], [[Streaming SIMD Extensions|SSE]]
* [[Socket A]] (EV6)
* [[Front-side bus]]: 166/200&nbsp;MHz (333/400&nbsp;MT/s)
* Vcore: 1.65&nbsp;V
* First release: February 10, 2003
* Clock rate: 1833–2333&nbsp;MHz (2500+ to 3200+)
** 133&nbsp;MHz FSB: 1867–2133&nbsp;MHz (2500+ to 2800+); uncommon
** 166&nbsp;MHz FSB: 1833–2333&nbsp;MHz (2500+ to 3200+)
** 200&nbsp;MHz FSB: 2100, 2200&nbsp;MHz (3000+, 3200+)

''Thorton (130&nbsp;nm)''
* L1-cache: 64 + 64&nbsp;KB (Data + Instructions)
* L2-cache: 256&nbsp;KB, full speed
* [[MMX (instruction set)|MMX]], [[3DNow!]], [[Streaming SIMD Extensions|SSE]]
* [[Socket A]] (EV6)
* [[Front-side bus]]: 133/166/200&nbsp;MHz (266/333/400&nbsp;MT/s)
* Vcore: 1.50–1.65&nbsp;V
* First release: September 2003
* Clock rate: 1667–2200&nbsp;MHz (2000+ to 3100+)
** 133&nbsp;MHz FSB: 1600–2133&nbsp;MHz (2000+ to 2600+)
** 166&nbsp;MHz FSB: 2083&nbsp;MHz (2600+)
** 200&nbsp;MHz FSB: 2200&nbsp;MHz (3100+)