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===SH-2A=== The SH-2A is an upgrade to the SH-2 core that added some 32-bit instructions. It was announced in early 2006. New features on the SH-2A core include: * Superscalar architecture: execution of 2 instructions simultaneously * [[Harvard architecture]] * Two 5-stage pipelines * Mixed 16-bit and 32-bit instructions * 15 register banks for interrupt response in 6 cycles. * Optional FPU The SH-2A family today spans a wide memory field from 16 KB up to and includes many ROM-less variations. The devices feature standard peripherals such as [[Controller-area network|CAN]], [[Ethernet]], [[USB]] and more as well as more application-specific peripherals such as [[Motor controller|motor control]] timers, [[Thin-film transistor|TFT]] controllers and peripherals dedicated to automotive powertrain applications.
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