Editing Intel 4004 (section)

== Technical specifications ==
{{more citations needed|section|date=November 2017}}<!-- most of this section is not cited -->
[[File:4004 arch.svg|thumb|Intel 4004 architectural block diagram]]
[[File:Intel 4004 processor pinout.png|thumb|Intel 4004 DIP chip [[pinout]]]]
[[File:Intel 4004 open.jpg|thumb|Open Intel 4004 processor]]

{| class="infobox" style="font-size:88%;width:23em;"
|-
|+ Intel 4004 registers
|-
|
{| style="font-size:88%;"
|- style="width:10px; text-align:center;"
| <sup>1</sup><sub>1</sub>
| <sup>1</sup><sub>0</sub>
| <sup>0</sup><sub>9</sub>
| <sup>0</sup><sub>8</sub>
| <sup>0</sup><sub>7</sub>
| <sup>0</sup><sub>6</sub>
| <sup>0</sup><sub>5</sub>
| <sup>0</sup><sub>4</sub>
| <sup>0</sup><sub>3</sub>
| <sup>0</sup><sub>2</sub>
| <sup>0</sup><sub>1</sub>
| <sup>0</sup><sub>0</sub>
| style="width:auto;" | ''(bit position)''
|-
|colspan="13" | '''Accumulator'''
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="4"| &nbsp;
| style="text-align:center; background:white" colspan="4"| &nbsp;
| style="text-align:center;" colspan="4"| A
| style="width:auto; background:white; color:black;"| '''A'''ccumulator
|-
|colspan="13" | '''Index registers'''
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="4"| &nbsp;
| style="text-align:center;" colspan="4"| R0
| style="text-align:center;" colspan="4"| R1
| style="width:auto; background:white; color:black;"| &nbsp;
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="4"| &nbsp;
| style="text-align:center;" colspan="4"| R2
| style="text-align:center;" colspan="4"| R3
| style="width:auto; background:white; color:black;"| &nbsp;
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="4"| &nbsp;
| style="text-align:center;" colspan="4"| R4
| style="text-align:center;" colspan="4"| R5
| style="width:auto; background:white; color:black;"| &nbsp;
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="4"| &nbsp;
| style="text-align:center;" colspan="4"| R6
| style="text-align:center;" colspan="4"| R7
| style="width:auto; background:white; color:black;"| &nbsp;
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="4"| &nbsp;
| style="text-align:center;" colspan="4"| R8
| style="text-align:center;" colspan="4"| R9
| style="width:auto; background:white; color:black;"| &nbsp;
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="4"| &nbsp;
| style="text-align:center;" colspan="4"| R10
| style="text-align:center;" colspan="4"| R11
| style="width:auto; background:white; color:black;"| &nbsp;
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="4"| &nbsp;
| style="text-align:center;" colspan="4"| R12
| style="text-align:center;" colspan="4"| R13
| style="width:auto; background:white; color:black;"| &nbsp;
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="4"| &nbsp;
| style="text-align:center;" colspan="4"| R14
| style="text-align:center;" colspan="4"| R15
| style="width:auto; background:white; color:black;"| &nbsp;
|-
|colspan="13" | '''Program counter'''
|- style="background:silver;color:black"
| style="text-align:center;" colspan="12"| PC
| style="background:white; color:black;"| '''P'''rogram '''C'''ounter
|-
|colspan="13" | '''Push-down address call stack''' <br/>
|- style="background:silver;color:black"
| style="text-align:center;" colspan="12"| PC1
| style="background:white; color:black;"| Call level 1
|- style="background:silver;color:black"
| style="text-align:center;" colspan="12"| PC2
| style="background:white; color:black;"| Call level 2
|- style="background:silver;color:black"
| style="text-align:center;" colspan="12"| PC3
| style="background:white; color:black;"| Call level 3
|-
|colspan="13" | '''Condition codes'''
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="11" | &nbsp;
| style="text-align:center;"| C
| style="background:white; color:black" | [[Carry flag|'''C'''arry flag]]
|}
|}

<!-- PLEASE DON'T "CORRECT" THE CLOCK SPEED VALUE, IT IS CORRECT! -->
<!-- how come I just read an Intel datasheet that pegs it as "0.75MHz" and "750kHz", then? -->
* Maximum [[clock rate]] is 740&nbsp;[[kilohertz|kHz]]. The 4004 had this maximum clock rating upon its initial 1971 release.{{efn|reference=Although the early documentation states "0.75&nbsp;MHz", this is at odds with the timing diagrams, which specify a minimum overall cycle time of 1350&nbsp;ns (=741&nbsp;kHz) and a maximum of 2010&nbsp;ns (=498&nbsp;kHz).}}
* Instruction cycle time: minimum 10.8&nbsp;μs<ref name=i4004data/> (8 clock cycles per machine cycle).
* Instruction execution time 1 or 2 machine cycles (10.8 or 21.6&nbsp;μs), {{val|46250}} to {{val|92500}} instructions per second.
** Adding two 8-digit decimal numbers (32 bits each, assuming 4-bit BCD digits) takes a claimed 850&nbsp;μs, or approximately 79 machine cycles (632 clock ticks), for an average of just under 10 cycles (80 ticks) per digit pair and an operating speed of 1176 × 8-digit additions per second{{efn|This statistic comes from the same document as the "0.75&nbsp;MHz" claim and which appears to inaccurately round off the true figures for the purposes of summary. 850&nbsp;μs with a minimum 10.8&nbsp;μs cycle time would in truth be 78.7 machine cycles, or roughly 629 clock ticks. As the processor is locked into an 8-tick cycle, it is more likely that this operation would take 79 or even 80 full cycles, thus 632 to 640 ticks and 853 to 864&nbsp;μs (or 854 to 865&nbsp;μs at a true 740&nbsp;kHz), and reducing the actual execution speed to 1157–1172 (or 1156–1171) 8-digit additions per second.}}
* Separate program and data storage. Contrary to [[Harvard architecture]] designs, however, which use separate [[computer bus|bus]]es, the 4004, with its need to keep pin count down, uses a single [[multiplexer|multiplexed]] 4-bit bus for transferring:
** 12-bit addresses,
** 8-bit instructions,
** 4-bit data [[word (data type)|word]]s.
* Able to directly address 5120 bits (equivalent to 640 bytes) of RAM, stored as 1280 4-bit "characters" and organized into groups representing 1024 "data" and 256 "status" characters (512 and 128 bytes).{{efn|However, this could only be used as working / data memory, and was non-executable: program code could not be stored in or run from RAM, as the processor kept the two memory areas strictly segregated at the microcode level. Instruction fetching forced assertion of the ROM chip-select line (and deassertion of the RAM select lines), and the chip had no way to "write" data to anything other than an IO port whilst the ROM area was selected.}}
* Able to directly address {{val|32,768}} bits of ROM, equivalent to and arranged as 4096 8-bit words (i.e. bytes).{{efn|The only part of the 4004 memory space capable of storing executable code, though also usable for general-purpose storage.}}
* [[Instruction set]] contained 46 instructions (of which 41 were 8 bits wide and 5 were 16 bits wide).
* Register set contains an accumulator and 16 index registers of 4 bits each.
* Internal [[subroutine]] [[internal stack|stack]], 3 levels deep.

=== Logic levels ===
{|class=wikitable
! Symbol         !! Min.                        !! Max
|-
| V<sub>SS–DD</sub> || +15&nbsp;V − 5%          || +15&nbsp;V + 5%
|-
| V<sub>IL</sub> || V<sub>DD</sub>              || V<sub>SS</sub> − 5.5&nbsp;V
|-
| V<sub>IH</sub> || V<sub>SS</sub> − 1.5&nbsp;V || V<sub>SS</sub> + 0.3&nbsp;V
|-
| V<sub>OL</sub> || V<sub>SS</sub> − 12&nbsp;V  || V<sub>SS</sub> − 6.5&nbsp;V
|-
| V<sub>OH</sub> || V<sub>SS</sub> − 0.5&nbsp;V || V<sub>SS</sub>
|}

=== Support chips ===
* 4001: 256-[[byte]] ROM (256 8-bit ''program'' instructions) and one built-in 4-bit [[input/output|I/O]] port. A 4001 ROM+I/O chip cannot be used in a system along with a 4008/4009 pair.<ref>IMPORTANT section at page 25: http://www.intel.com/Assets/PDF/Manual/msc4.pdf.</ref>
* 4002: 40-byte [[random-access memory|RAM]] (80 4-bit ''data'' words) and one built-in 4-bit output port; the RAM portion of the chip is organized into 4 "registers" of 20 4-bit words:
** 16 data words (used for [[significand|mantissa]] digits in the original calculator design), accessed in a relatively standard manner,
** 4 status words (used for [[exponent]] digits and signs in the original calculator design), accessed using I/O type commands in place of the ROM's input channel.
* 4003: 10-bit parallel output [[shift register]] for scanning keyboards, displays, printers, etc.
* 4008: 8-bit address latch for access to standard memory chips and one built-in 4-bit chip-select and I/O port.
* 4009: program and I/O access converter to standard memory and I/O chips.
* 4269: keyboard/display interface.
* 4289: memory interface (combined functions of 4008 and 4009).

The minimum system specification described by Intel consists of a 4004 with a single 256-byte 4001 program ROM; there is no explicit need for separate RAM in minimal-complexity applications thanks to the 4004's large number of onboard index registers, which represent the equivalent of 16&nbsp;× 4-bit or 8&nbsp;× 8-bit characters (or a mixture) of working RAM, nor for simple interface chips thanks to the ROM's built-in I/O lines. However, as project complexity increases, the various other support chips start to become useful.

===Packaging===
Numerous versions of the Intel MCS-4 line of processors were produced. The earliest versions, marked C (like C4004), were ceramic and used a zebra pattern of white and gray on the back of the chips, often called "grey traces". The next generation of the chips was plain white ceramic (also marked C), and then dark gray ceramic (D). Many of the more recent versions of MCS-4 family were also produced with plastic (P).

<gallery mode="packed">
Intel_C4004_b.jpg|The ceramic C4004 variant without gray traces
Intel_D4004.jpg|The ceramic D4004 variant
Intel_P4004.jpg|The plastic P4004 variant
</gallery>

{{clear|both}}