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=== Design === The Blue Gene/Q "compute chip" is based on the [[64-bit]] [[IBM A2]] processor core. The A2 processor core is 4-way [[simultaneous multithreading|simultaneously multithreaded]] and was augmented with a [[SIMD]] quad-vector [[double-precision floating-point format|double-precision]] [[floating-point arithmetic|floating-point]] unit (IBM QPX). Each Blue Gene/Q compute chip contains 18 such A2 processor cores, running at 1.6 GHz. 16 Cores are used for application computing and a 17th core is used for handling operating system assist functions such as [[interrupt]]s, [[asynchronous I/O]], [[Message Passing Interface|MPI]] pacing, and [[Reliability, availability and serviceability|RAS]]. The 18th core is a [[redundancy (engineering)|redundant]] manufacturing spare, used to increase yield. The spared-out core is disabled prior to system operation. The chip's processor cores are linked by a crossbar switch to a 32 MB [[eDRAM]] L2 cache, operating at half core speed. The L2 cache is multi-versioned—supporting [[transactional memory]] and [[speculative execution]]—and has hardware support for [[atomic operations]].<ref name="PACT11">{{cite web |title=Memory Speculation of the Blue Gene/Q Compute Chip |url=http://wands.cse.lehigh.edu/IBM_BQC_PACT2011.ppt |access-date=2011-12-23 }}</ref> L2 cache misses are handled by two built-in [[DDR3]] memory controllers running at 1.33 GHz. The chip also integrates logic for chip-to-chip communications in a 5D [[Torus interconnect|torus]] configuration, with 2 GB/s chip-to-chip links. The Blue Gene/Q chip is manufactured on IBM's copper SOI process at 45 nm. It delivers a peak performance of 204.8 GFLOPS while drawing approximately 55 watts. The chip measures 19×19 mm (359.5 mm²) and comprises 1.47 billion transistors. Completing the compute node, the chip is mounted on a compute card along with 16 GB [[DDR3]] [[DRAM]] (i.e., 1 GB for each user processor core).<ref name="HotChips11">{{cite web |title=The Blue Gene/Q Compute chip |url=http://www.hotchips.org/wp-content/uploads/hc_archives/hc23/HC23.18.1-manycore/HC23.18.121.BlueGene-IBM_BQC_HC23_20110818.pdf |access-date=2011-12-23 |archive-date=2015-04-29 |archive-url=https://web.archive.org/web/20150429070233/http://www.hotchips.org/wp-content/uploads/hc_archives/hc23/HC23.18.1-manycore/HC23.18.121.BlueGene-IBM_BQC_HC23_20110818.pdf |url-status=dead }}</ref> A Q32<ref>{{cite web|url=http://www-01.ibm.com/common/ssi/rep_ca/8/897/ENUS112-028/ENUS112-028.PDF|title=IBM Blue Gene/Q supercomputer delivers petascale computing for high-performance computing applications|website=01.ibm.com|access-date=13 October 2017}}</ref> "compute drawer" contains 32 compute nodes, each water cooled.<ref name="TheRegSC10">{{cite web |title=IBM uncloaks 20 petaflops BlueGene/Q super |website=The Register |date=2010-11-22 |url=https://www.theregister.co.uk/2010/11/22/ibm_blue_gene_q_super/ |access-date=2010-11-25}}</ref> A "midplane" (crate) contains 16 Q32 compute drawers for a total of 512 compute nodes, electrically interconnected in a 5D torus configuration (4x4x4x4x2). Beyond the midplane level, all connections are optical. Racks have two midplanes, thus 32 compute drawers, for a total of 1024 compute nodes, 16,384 user cores, and 16 TB RAM.<ref name="TheRegSC10" /> Separate I/O drawers, placed at the top of a rack or in a separate rack, are air cooled and contain 8 compute cards and 8 PCIe expansion slots for [[InfiniBand]] or [[10 Gigabit Ethernet]] networking.<ref name="TheRegSC10" />
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