Editing IBM 1620 (section)

==Model II==
The '''IBM 1620 Model II''' (commonly called simply the Model II) was a vastly improved implementation, compared to the original [[#Model I|Model I]]. The Model II was introduced in 1962.

* It had basic [[arithmetic logic unit|ALU]] hardware for addition and subtraction, but multiplication was still done by [[core memory|in-core memory]] table lookup, using a 200-digit table (at address 00100..00299).  [[core memory|Memory addresses]] at address 00300..00399 were freed by the replacement of the addition table with hardware, resulting in storage of two selectable "bands" of seven five-digit [[index register]]s.
* Rather than being an available option, as in the Model I, the divide hardware using a repeated subtraction algorithm, was built in. [[Floating-point arithmetic]] was an available option, as were octal input/output, logical operations, and base conversion to/from decimal instructions.
* The entire core memory was in the IBM 1625 memory unit. Memory cycle time was halved compared to the Model I's (internal or 1623 memory unit), to 10&nbsp;[[microsecond|μs]] (i.e., the cycle speed was raised to 100&nbsp;[[kilohertz|kHz]]) by using faster cores.<ref name=NordBook/> A Memory Address Register Storage (MARS) core memory read, clear, or write operation took 1.5&nbsp;μs and each write operation was automatically (but not necessarily immediately) preceded by a read or clear operation of the same "register(s)" during the 10&nbsp;μs memory cycle.
* The processor clock speed was also doubled, to 2&nbsp;[[megahertz|MHz]], which was still divided by 20 by a 10 position [[ring counter]] to provide the system timing/control signals. The fetch/execute mechanism was completely redesigned, optimizing the timing and allowing partial fetches when the P or Q fields were not needed. Instructions took either 1, 4, or 6 memory cycles (10&nbsp;μs, 40&nbsp;μs, or 60&nbsp;μs) to fetch and a variable number of memory cycles to execute. Indirect addressing<ref name=IBM.intro59/> added three memory cycles (30&nbsp;μs) for each level of [[indirection]]. Indexed addressing added five memory cycles (50&nbsp;μs) for each level of indexing. Indirect and indexed addressing could be combined at any level of indirection or indexing.<ref>"Multi-level indirection could be used (you could even put the machine in an infinite indirect addressing loop), and in the middle three digits of five-digit addresses (on the 1620 II) they were set to select one of seven index registers. {{cite book    |url=https://books.google.com/books?isbn=1456751158  |isbn=978-1456751159
|title=History of Computer Graphics  |publisher=DLR Associates Series  
|author=Dan Ryan  |date=2011}}</ref>