Editing Endianness (section)

=== Bi-endianness ===

Some instruction set architectures feature a setting which allows for switchable endianness in data fetches and stores, instruction fetches, or both; those instruction set architectures are referred to as ''bi-endian''. Architectures that support switchable endianness include [[PowerPC]]/[[Power ISA]], [[SPARC]] V9, [[ARM architecture|ARM]] versions 3 and above, [[DEC Alpha]], [[MIPS architecture|MIPS]], [[Intel i860]], [[PA-RISC]], [[SuperH|SuperH SH-4]], [[IA-64]], [[C-Sky]], and [[RISC-V]]. This feature can improve performance or simplify the logic of networking devices and software. The word ''bi-endian'', when said of hardware, denotes the capability of the machine to compute or pass data in either endian format.

Many of these architectures can be switched via software to default to a specific endian format (usually done when the computer starts up); however, on some systems, the default endianness is selected by hardware on the motherboard and cannot be changed via software (e.g. Alpha, which runs only in big-endian mode on the [[Cray T3E]]).

[[IBM AIX]] and [[IBM i]] run in big-endian mode on bi-endian Power ISA; [[Linux]] originally ran in big-endian mode, but by 2019, IBM had transitioned to little-endian mode for Linux to ease the porting of Linux software from x86 to Power.<ref>{{cite web |title=Little endian and Linux on IBM Power Systems |url=https://developer.ibm.com/articles/l-power-little-endian-faq-trs/ |date=2016-06-16 |website=IBM |author=Jeff Scheel |access-date=2022-03-27 |archive-date=2022-03-27 |archive-url=https://web.archive.org/web/20220327025540/https://developer.ibm.com/articles/l-power-little-endian-faq-trs/ |url-status=live }}</ref><ref>{{cite web |last1=Timothy Prickett Morgan |title=The Transition To RHEL 8 Begins On Power Systems |url=https://www.itjungle.com/2019/06/10/the-transition-to-rhel-8-begins-on-power-systems/ |website=ITJungle |date=10 June 2019 |access-date=26 March 2022 |archive-date=24 January 2022 |archive-url=https://web.archive.org/web/20220124063316/https://www.itjungle.com/2019/06/10/the-transition-to-rhel-8-begins-on-power-systems/ |url-status=live }}</ref> SPARC has no relevant little-endian deployment, as both [[Oracle Solaris]] and Linux run in big-endian mode on bi-endian SPARC systems, and can be considered big-endian in practice. ARM, C-Sky, and RISC-V have no relevant big-endian deployments, and can be considered little-endian in practice.

The term ''bi-endian'' refers primarily to how a processor treats data accesses. Instruction accesses (fetches of instruction words) on a given processor may still assume a fixed endianness, even if data accesses are fully bi-endian, though this is not always the case, such as on Intel's [[IA-64]]-based Itanium CPU, which allows both.

Some nominally bi-endian CPUs require motherboard help to fully switch endianness. For instance, the 32-bit desktop-oriented [[PowerPC]] processors in little-endian mode act as little-endian from the point of view of the executing programs, but they require the motherboard to perform a 64-bit swap across all 8 byte lanes to ensure that the little-endian view of things will apply to [[I/O]] devices. In the absence of this unusual motherboard hardware, device driver software must write to different addresses to undo the incomplete transformation and also must perform a normal byte swap.{{or|date=November 2023}}

Some CPUs, such as many PowerPC processors intended for embedded use and almost all SPARC processors, allow per-page choice of endianness.

SPARC processors since the late 1990s (SPARC v9 compliant processors) allow data endianness to be chosen with each individual instruction that loads from or stores to memory.

The [[ARM architecture]] supports two big-endian modes, called ''BE-8'' and ''BE-32''.<ref>{{cite web|title=Differences between BE-32 and BE-8 buses|url=http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0290g/ch06s05s01.html|access-date=2019-02-10|archive-date=2019-02-12|archive-url=https://web.archive.org/web/20190212070549/http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0290g/ch06s05s01.html|url-status=live}}</ref> CPUs up to ARMv5 only support BE-32 or word-invariant mode. Here any naturally aligned 32-bit access works like in little-endian mode, but access to a byte or 16-bit word is redirected to the corresponding address and unaligned access is not allowed. ARMv6 introduces BE-8 or byte-invariant mode, where access to a single byte works as in little-endian mode, but accessing a 16-bit, 32-bit or (starting with ARMv8) 64-bit word results in a byte swap of the data. This simplifies unaligned memory access as well as memory-mapped access to registers other than 32-bit.

Many processors have instructions to convert a word in a register to the opposite endianness, that is, they swap the order of the bytes in a 16-, 32- or 64-bit word. 

Recent Intel x86 and x86-64 architecture CPUs have a MOVBE instruction ([[Intel Core]] since generation 4, after [[Intel Atom|Atom]]),<ref>{{cite web |title = How to detect New Instruction support in the 4th generation Intel® Core™ processor family |url = https://software.intel.com/sites/default/files/article/405250/how-to-detect-new-instruction-support-in-the-4th-generation-intel-core-processor-family.pdf |access-date = 2 May 2017 |archive-date = 20 March 2016 |archive-url = https://web.archive.org/web/20160320222513/https://software.intel.com/sites/default/files/article/405250/how-to-detect-new-instruction-support-in-the-4th-generation-intel-core-processor-family.pdf |url-status = live }}</ref> which fetches a big-endian format word from memory or writes a word into memory in big-endian format. These processors are otherwise thoroughly little-endian.

There are also devices which use different formats in different places. For instance, the BQ27421 [[Texas Instruments]] battery gauge uses the little-endian format for its registers and the big-endian format for its [[random-access memory]].

[[SPARC]] historically used big-endian until version 9, which is bi-endian. Similarly early IBM POWER processors were big-endian, but the [[PowerPC]] and [[Power ISA]] descendants are now bi-endian. The [[ARM architecture]] was little-endian before version 3 when it became bi-endian.