Editing DIMM (section)

== Speeds ==
For various technologies, there are certain bus and device clock frequencies that are standardized; there is also a decided nomenclature for each of these speeds for each type.

DIMMs based on Single Data Rate (SDR) DRAM have the same bus frequency for data, address and control lines. DIMMs based on [[Double Data Rate]] (DDR) DRAM have data but not the strobe at double the rate of the clock; this is achieved by clocking on both the rising and falling edge of the data strobes. Power consumption and voltage gradually became lower with each generation of DDR-based DIMMs.

Another influence is Column Access Strobe (CAS) latency, or CL, which affects memory access speed. This is the delay time between the READ command and the moment data is available. See main article [[CAS latency|CAS/CL]].

{{Col-float|width=50em}}
{{Table alignment}}
{| class="wikitable plainrowheaders defaultright col1left col2left" style="margin-right: 2em;"
|+ [[SDR SDRAM]] DIMMs
|-
! scope="col" | Chip
! scope="col" | Module
! scope="col" | [[Clock rate|Effective clock]]<br/>({{abbr|MHz|megaherz}})
! scope="col" | [[Transfer (computing)|Transfer rate]]<br/>([[Transfers per second|{{abbr|MT/s|megatransfers per second}}]])
! scope="col" | Voltage<br/>([[Volt|{{abbr|V|volt}}]])
|-
! scope="row" | SDR-66
| PC-66 || 66 || 66 || 3.3
|-
! scope="row" | SDR-100
| PC-100 || 100 || 100|| 3.3
|-
! scope="row" | SDR-133
| PC-133 || 133 || 133 || 3.3
|}

{{Table alignment}}
{| class="wikitable plainrowheaders defaultright col1left col2left" style="margin-right: 2em;"
|+ [[DDR SDRAM]] (DDR1) DIMMs
|-
! scope="col" | Chip
! scope="col" | Module
! scope="col" | Memory clock<br/>({{abbr|MHz|megaherz}})
! scope="col" | I/O bus clock<br/>({{abbr|MHz|megaherz}})
! scope="col" | [[Transfer (computing)|Transfer rate]]<br/>([[Transfers per second|{{abbr|MT/s|megatransfers per second}}]])
! scope="col" | Voltage<br/>([[Volt|{{abbr|V|volt}}]])
|-
! scope="row" | DDR-200
| PC-1600 || 100 || 100 || 200 || 2.5
|-
! scope="row" | DDR-266
| PC-2100 || 133 || 133 || 266 || 2.5
|-
! scope="row" | DDR-333
| PC-2700 || 166 || 166 || 333 || 2.5
|-
! scope="row" | DDR-400
| PC-3200 || 200 || 200 || 400 || 2.6
|}

{{Table alignment}}
{| class="wikitable plainrowheaders defaultright col1left col2left" style="margin-right: 2em;"
|+ [[DDR2 SDRAM]] DIMMs
|-
! scope="col" | Chip
! scope="col" | Module
! scope="col" | Memory clock<br/>({{abbr|MHz|megaherz}})
! scope="col" | I/O bus clock<br/>({{abbr|MHz|megaherz}})
! scope="col" | [[Transfer (computing)|Transfer rate]]<br/>([[Transfers per second|{{abbr|MT/s|megatransfers per second}}]])
! scope="col" | Voltage<br/>([[Volt|{{abbr|V|volt}}]])
|-
! scope="row" | DDR2-400
| PC2-3200 || 100 || 200 || 400 || 1.8
|-
! scope="row" | DDR2-533
| PC2-4200 || 133 || 266 || 533 || 1.8
|-
! scope="row" | DDR2-667
| PC2-5300 || 166 || 333 || 667 || 1.8
|-
! scope="row" | DDR2-800
| PC2-6400 || 200 || 400 || 800 || 1.8
|-
! scope="row" | {{nowrap|DDR2-1066}}
| {{nowrap|PC2-8500}} || 266 || 533 || 1066 || 1.8
|}

{{Col-float-break|width=60em}}

{{Table alignment}}
{| class="wikitable plainrowheaders defaultright col1left col2left"
|+ [[DDR3 SDRAM]] DIMMs
|-
! scope="col" | Chip
! scope="col" | Module
! scope="col" | Memory clock<br/>({{abbr|MHz|megaherz}})
! scope="col" | I/O bus clock<br/>({{abbr|MHz|megaherz}})
! scope="col" | [[Transfer (computing)|Transfer rate]]<br/>([[Transfers per second|{{abbr|MT/s|megatransfers per second}}]])
! scope="col" | Voltage<br/>([[Volt|{{abbr|V|volt}}]])
|-
! scope="row" | DDR3-800
| PC3-6400 || 100 || 400 || 800 || 1.5
|-
! scope="row" | DDR3-1066
| PC3-8500 || 133 || 533 || 1066 || 1.5
|-
! scope="row" | DDR3-1333
| PC3-10600 || 166 || 667 || 1333 || 1.5
|-
! scope="row" | DDR3-1600
| PC3-12800 || 200 || 800 || 1600 || 1.5
|-
! scope="row" | DDR3-1866
| PC3-14900 || 233 || 933 || 1866 || 1.5
|-
! scope="row" | DDR3-2133
| PC3-17000 || 266 || 1066 || 2133 || 1.5
|-
! scope="row" | DDR3-2400
| PC3-19200 || 300 || 1200 || 2400 || 1.5
|}

{{Table alignment}}
{| class="wikitable plainrowheaders defaultright col1left col2left" style="margin-right: 2em;"
|+ [[DDR4 SDRAM]] DIMMs
|-
! scope="col" | Chip
! scope="col" | Module
! scope="col" | Memory clock<br/>({{abbr|MHz|megaherz}})
! scope="col" | I/O bus clock<br/>({{abbr|MHz|megaherz}})
! scope="col" | [[Transfer (computing)|Transfer rate]]<br/>([[Transfers per second|{{abbr|MT/s|megatransfers per second}}]])
! scope="col" | Voltage<br/>([[Volt|{{abbr|V|volt}}]])
|-
! scope="row" | DDR4-1600
| PC4-12800 || 200 || 800 || 1600 || 1.2
|-
! scope="row" | DDR4-1866
| PC4-14900 || 233 || 933 || 1866 || 1.2
|-
! scope="row" | DDR4-2133
| PC4-17000 || 266 || 1066 || 2133 || 1.2
|-
! scope="row" | DDR4-2400
| PC4-19200 || 300 || 1200 || 2400 || 1.2
|-
! scope="row" | DDR4-2666
| PC4-21300 || 333 || 1333 || 2666 || 1.2
|-
! scope="row" | DDR4-3200
| PC4-25600 || 400 || 1600 || 3200 || 1.2
|}

{{Table alignment}}
{| class="wikitable plainrowheaders defaultright col1left col2left" style="margin-right: 2em;"
|+ [[DDR5 SDRAM]] DIMMs
|-
! scope="col" | Chip
! scope="col" | Module
! scope="col" | Memory clock<br/>({{abbr|MHz|megaherz}})
! scope="col" | I/O bus clock<br/>({{abbr|MHz|megaherz}})
! scope="col" | [[Transfer (computing)|Transfer rate]]<br/>([[Transfers per second|{{abbr|MT/s|megatransfers per second}}]])
! scope="col" | Voltage<br/>([[Volt|{{abbr|V|volt}}]])
|-
! scope="row" | DDR5-4000
| PC5-32000 || 2000 || 2000 || 4000 || 1.1
|-
! scope="row" | DDR5-4400
| PC5-35200 || 2200 || 2200 || 4400 || 1.1
|-
! scope="row" | DDR5-4800
| PC5-38400 || 2400 || 2400 || 4800 || 1.1
|-
! scope="row" | DDR5-5200
| PC5-41600 || 2600 || 2600 || 5200 || 1.1
|-
! scope="row" | DDR5-5600
| PC5-44800 || 2800 || 2800 || 5600 || 1.1
|-
! scope="row" | DDR5-6000
| PC5-48000 || 3000 || 3000 || 6000 || 1.1
|-
! scope="row" | DDR5-6200
| PC5-49600 || 3100 || 3100 || 6200 || 1.1
|-
! scope="row" | DDR5-6400
| PC5-51200 || 3200 || 3200 || 6400 || 1.1
|-
! scope="row" | DDR5-6800
| PC5-54400 || 3400 || 3400 || 6800 || 1.1
|-
! scope="row" | DDR5-7200
| PC5-57600 || 3600 || 3600 || 7200 || 1.1
|-
! scope="row" | DDR5-7600
| PC5-60800 || 3800 || 3800 || 7600 || 1.1
|-
! scope="row" | DDR5-8000
| PC5-64000 || 4000 || 4000 || 8000 || 1.1
|-
! scope="row" | DDR5-8400
| PC5-67200 || 4200 || 4200 || 8400 || 1.1
|-
! scope="row" | DDR5-8800
| PC5-70400 || 4400 || 4400 || 8800 || 1.1
|}

{{Col-float-end}}