Editing Counter (digital) (section)

====Synchronous binary counter====

The circuit shown below is a synchronous, up-counting four-bit binary counter implemented with JK flip-flops. Upon clock rising edge, bit 0 will always toggle, whereas other bits will toggle only when all less-significant bits are at a logic high state (i.e., Q1 toggles if Q0 is logic high; Q2 toggles if Q0 and Q1 are both high; and Q3 toggles if Q0, Q1, and Q2 are all high).

[[File:4 bit binary synchronous counter.svg|400px|border|Synchronous 4-bit binary counter using JK flip-flops]]

As in asynchronous counters, each flip-flop introduces a delay from input clock edge to output toggle, but in this case all flip-flops change state concurrently, and consequently the counter output will settle after only one flip-flop delay regardless of the number of bits.