Editing Transmeta Crusoe (section)

== Design ==
[[File:Transmeta TM5600.jpg|thumb|A Transmeta CPU from a Fujitsu Lifebook P series laptop]]
[[File:Efficeon.jpg|thumb|alt=Transmeta Efficeon|Transmeta Efficeon (TM8000)]]

The Crusoe is notable for its method of achieving x86 compatibility. Instead of the instruction set architecture being implemented in hardware, or translated by specialized hardware, the Crusoe runs a software abstraction layer, or a [[virtual machine]], known as the [[Code Morphing Software]] (CMS). The CMS translates [[machine code]] instructions received from programs into native instructions for the microprocessor. In this way, the Crusoe can [[software emulation|emulate]] other [[instruction set architecture]]s (ISAs). This is used to allow the microprocessors to emulate the Intel [[x86 instruction set]]. In theory, it is possible for the CMS to be modified to emulate other ISAs. Transmeta demonstrated Crusoe executing [[Java bytecode]] by translating the bytecodes into instructions in its native instruction set. The addition of an abstraction layer between the x86 instruction stream and the hardware means that the hardware architecture can change without breaking compatibility, just by modifying the CMS. For example, [[Transmeta Efficeon]] — a second-generation Transmeta design — has a 256-bit-wide [[VLIW]] core versus the 128-bit core of the Crusoe. Efficeon also supports SSE instructions.

The Crusoe is a [[VLIW]] microprocessor that executes bundles of instructions, termed ''molecules'' by Transmeta. Each ''molecule'' contains multiple instructions, termed ''atoms''. The Code Morphing Software translates x86 instructions into native instructions. The native instructions are 32 bits long. Instructions that meet a set of conditions can be executed simultaneously and are combined to form a 64- or 128-bit ''molecule'' containing two or four ''atoms'', respectively. In the event that there are not enough instructions to fill a molecule, the software inserts [[NOP (code)|NOP]]s as padding to fill out empty slots. This is required in all VLIW architectures and is criticised for being inefficient, which is why there are ''molecules'' of two separate lengths.

The Crusoe performs in software some of the functionality traditionally implemented in hardware (e.g. instruction re-ordering), resulting in simpler hardware with fewer [[transistor]]s. The relative simplicity of the hardware means that Crusoe consumes less power (and therefore generates less heat) than other x86-compatible microprocessors running at the same frequency. A 700&nbsp;MHz Crusoe ran x86 programs at the speed of a 500&nbsp;MHz Pentium III x86 processor,<ref name="ref1">{{cite web|url=http://news.cnet.com/Transmeta-Are-the-chips-down/2100-1006_3-275353.html|title=Transmeta: Are the chips down?|first1=Michael|last1=Kanellos|first2=Rachel|last2=Konrad|publisher=[[CNET]]|date=November 5, 2001}}</ref> although the Crusoe processor was smaller and cheaper than the corresponding Intel processor.<ref name="ref1"/>

The Crusoe was initially available in two forms: the TM3120 (later called TM3200) for embedded applications and the TM5400 for low-power personal computing.<ref>{{Cite web |date=2000-02-29 |title=Crusoe - a new world of mobility from Transmeta |url=http://www.transmeta.com:80/crusoe/family.html |access-date=2023-08-10 |archive-url=https://web.archive.org/web/20000229090310/http://www.transmeta.com:80/crusoe/family.html |archive-date=2000-02-29 }}</ref> Both were based on the same architecture but differed in clock frequency and peripheral support. The TM3120/TM3200 were manufactured in speeds of 333(TM3120 only) 366 and, 400&nbsp;MHz using a 220&nbsp;nm process.<ref name=":1">{{Cite web |title=The Technology Behind Crusoe Processors |url=https://classes.engineering.wustl.edu/cse362/images/c/c7/Paper_aklaiber_19jan00.pdf |website=Washington University in St. Louise SCHOOL OF ENGINEERING AND APPLIED SCIENCE}}</ref><ref name=":2">{{Cite web |title=TM3120_DataSheet_1-18-00.pdf |url=http://www.transmeta.com/crusoe/download/pdf/TM3120_DataSheet_1-18-00.pdf |url-status=dead |archive-url=https://web.archive.org/web/20000819002430/http://www.transmeta.com/crusoe/download/pdf/TM3120_DataSheet_1-18-00.pdf |archive-date=2000-08-19 |access-date=2023-08-10 |website=Transmeta}}</ref><ref name=":3">{{Cite web |title=TM3200_ProductBrief_5-20-00.pdf |url=http://www.transmeta.com/crusoe/download/pdf/TM3200_ProductBrief_5-20-00.pdf |url-status=dead |archive-url=https://web.archive.org/web/20000818000537/http://www.transmeta.com/crusoe/download/pdf/TM3200_ProductBrief_5-20-00.pdf |archive-date=2000-08-18 |access-date=2023-08-10 |website=Transmeta}}</ref> It has a 96k L1 cache (64&nbsp;KB instruction and 32&nbsp;KB data) and no L2 cache. The TM3120/TM3200 has an integrated [[SDRAM]] [[memory controller]] and a [[Conventional PCI|PCI]] interface. It measures 77&nbsp;mm<sup>2</sup> and uses a 1.5&nbsp;V power supply, dissipating less than 1.5&nbsp;W of power (typically).<ref name=":1" /><ref name=":2" /><ref name=":3" /> The TM5400 differs from the TM3120/TM3200 with the inclusion of a 128K of L1 Cache(with the addition of 32&nbsp;KB data cache) as well as the addition of DDR memory support, 256&nbsp;KB unified L2 cache and LongRun power reduction technology manufactured using a smaller 180&nbsp;nm process.<ref name=":1" /><ref name=":0">{{Cite web |title=TM5400_DataSheet_1-18-00.pdf |url=http://www.transmeta.com/crusoe/download/pdf/TM5400_DataSheet_1-18-00.pdf |url-status=dead |archive-url=https://web.archive.org/web/20000819002436/http://www.transmeta.com:80/crusoe/download/pdf/TM5400_DataSheet_1-18-00.pdf |archive-date=2000-08-19}}</ref> It measures 73&nbsp;mm<sup>2</sup> and uses a 1.10&nbsp;V (f = 25%) and 1.6&nbsp;V (f = 100%) power supply, dissipating 0.5–1.5&nbsp;W typically and a maximum of 6&nbsp;W.<ref name=":1" /><ref name=":0" /> Later the TM5600 was introduced as a higher end offering to the TM5400 with double the L2 cache (512&nbsp;KB vs 256&nbsp;KB).<ref name=":0" /><ref>{{Cite web |title=tm5400n5600_databook_001101.pdf |url=http://transmeta.com/crusoe_docs/tm5400n5600_databook_001101.pdf |url-status=dead |archive-url=https://web.archive.org/web/20031214014530/http://transmeta.com/crusoe_docs/tm5400n5600_databook_001101.pdf |archive-date=2003-12-14 |access-date=2023-08-10 |website=Transmeta}}</ref><ref>{{Cite web |title=tm5600_productbrief_000802.pdf |url=http://transmeta.com:80/crusoe_docs/tm5600_productbrief_000802.pdf |url-status=dead |archive-url=https://web.archive.org/web/20031214103237/http://transmeta.com/crusoe_docs/tm5600_productbrief_000802.pdf |archive-date=2003-12-14 |access-date=2023-08-10 |website=Transmeta}}</ref> Both the TM5400 and TM5600 operated at clock frequencies of 500–700&nbsp;MHz.<ref name=":4">{{Cite web |date=2000-11-15 |title=Crusoe - a new world of mobility from Transmeta |url=http://www.transmeta.com/crusoe/family.html |access-date=2023-08-10 |archive-url=https://web.archive.org/web/20001115093400/http://www.transmeta.com/crusoe/family.html |archive-date=2000-11-15 }}</ref>

The TM5500/TM5800 are die shrunk versions of the TM5400/5600 Built on a TSMC 130&nbsp;nm process at clock frequencies of 667-1000&nbsp;MHz.<ref>{{Cite web |date=2003-12-11 |title=Transmeta Corporation : Crusoe > Specifications > Crusoe TM5500 Processor |url=http://transmeta.com:80/crusoe/crusoe_tm5500.html |access-date=2023-08-10 |archive-url=https://web.archive.org/web/20031211134237/http://transmeta.com:80/crusoe/crusoe_tm5500.html |archive-date=2003-12-11 }}</ref><ref>{{Cite web |date=2003-10-17 |title=Transmeta Corporation : Crusoe > Specifications > Crusoe TM5800 Processor |url=http://www.transmeta.com:80/crusoe/crusoe_tm5800.html |access-date=2023-08-10 |archive-url=https://web.archive.org/web/20031017144537/http://www.transmeta.com:80/crusoe/crusoe_tm5800.html |archive-date=2003-10-17 }}</ref><ref name=":5">{{Cite web |title=tmta_processor_comparison.pdf |url=https://web.archive.org/web/20070101015549/http://www.transmeta.com:80/pdfs/brochures/tmta_processor_comparison.pdf |url-status=dead |archive-url=https://web.archive.org/web/20050513215251/http://www.transmeta.com/pdfs/brochures/tmta_processor_comparison.pdf |archive-date=2005-05-13 |access-date=2023-08-10 |website=Transmeta}}</ref> Embedded versions rated for 10 years of continuous use were marketed as Crusoe SE (for Special Embedded) TM55E/TM58E respectively at clock frequencies of 667-993&nbsp;MHz.<ref>{{Cite web |title=embedded_apps_030904.pdf |url=http://www.transmeta.com:80/pdfs/brochures/embedded_apps_030904.pdf |url-status=dead |archive-url=https://web.archive.org/web/20031118074614/http://www.transmeta.com:80/pdfs/brochures/embedded_apps_030904.pdf |archive-date=2003-11-18 |website=Transmeta}}</ref>

The TM5700/TM5900 removes SDRAM support for its integrated memory controller and now comes in a 54% smaller 399 pin FC-OBGA package rather than the ceramic 479 BGA package used previously.<ref name=":4" /><ref name=":5" /><ref>{{Cite web |date=2006-02-14 |title=Transmeta Corporation : Crusoe > Specifications > Crusoe TM5900/TM5700 Processors |url=http://www.transmeta.com:80/crusoe/crusoe_tm5900_tm5700.html |access-date=2023-08-10 |archive-url=https://web.archive.org/web/20060214152402/http://www.transmeta.com:80/crusoe/crusoe_tm5900_tm5700.html |archive-date=2006-02-14 }}</ref> Clock speed remains the same between 667 and 1000&nbsp;MHz.<ref>{{Cite web |title=crusoe_tm5700-tm5900_processor.pdf |url=http://www.transmeta.com/pdfs/brochures/crusoe_tm5700-tm5900_processor.pdf |url-status=dead |archive-url=https://web.archive.org/web/20050513215933/http://www.transmeta.com/pdfs/brochures/crusoe_tm5700-tm5900_processor.pdf |archive-date=2005-05-13 |access-date=2023-08-10 |website=Transmeta}}</ref>