Editing Superscalar processor (section)

==History==
[[Seymour Cray]]'s [[CDC 6600]] from 1964, while not capable of issuing multiple instructions per cycle, is often cited as an early influence to modern superscalar processors for its ability to execute instructions simultaneously through multiple functional units. The 1967 [[IBM System/360 Model 91]], was another early influence that introduced out-of-order execution, pioneering use of [[Tomasulo's algorithm]].<ref>{{cite journal |last1=Smith |first1=James E. |last2=Sohi |first2=Gurindar S. |title=The Microarchitecture of Superscalar Processors |journal=Proceedings of the IEEE |date=December 1995 |volume=83 |issue=12 |page=1609 |doi=10.1109/5.476078 |url=https://minds.wisconsin.edu/bitstream/handle/1793/9476/file_1.pdf}}</ref> The [[Intel i960]]CA (1989),<ref>{{cite conference |last1=McGeady |first1=Steven |title=The i960CA SuperScalar implementation of the 80960 architecture |journal=Digest of Papers Compcon Spring '90. |conference=Thirty-Fifth IEEE Computer Society International Conference on Intellectual Leverage |date=Spring 1990 |pages=232–240 |doi=10.1109/CMPCON.1990.63681|isbn=0-8186-2028-5 |s2cid=13206773 }}</ref> the [[AMD 29000]]-series 29050 (1990), and the Motorola [[MC88110]] (1991),<ref>{{cite book |last1=Diefendorff |first1=K. |last2=Allen |first2=M. |chapter=The Motorola 88110 Superscalar RISC microprocessor |title=Digest of Papers COMPCON Spring 1992 |date=Spring 1992 |pages=157–162 |doi=10.1109/CMPCON.1992.186702|isbn=0-8186-2655-0 |s2cid=34913907 }}</ref> microprocessors were the first commercial single-chip superscalar microprocessors. [[RISC]] microprocessors like these were the first to have superscalar execution, because RISC architectures free transistors and die area which can be used to include multiple execution units and the traditional uniformity of the instruction set favors superscalar dispatch (this was why RISC designs were faster than [[Complex instruction set computer|CISC]] designs through the 1980s and into the 1990s, and it's far more complicated to do multiple dispatch when instructions have variable bit length).

Except for CPUs used in [[Low-power electronics|low-power]] applications, [[embedded system]]s, and [[Battery (electricity)|battery]]-powered devices, essentially all general-purpose CPUs developed since about 1998 are superscalar.

The [[P5 (microarchitecture)|P5 Pentium]] was the first superscalar x86 processor; the [[Nx586]], [[P6 (microarchitecture)|P6 Pentium Pro]] and [[AMD K5]] were among the first designs which decode [[x86]]-instructions asynchronously into dynamic [[microcode]]-like ''[[micro-op]]'' sequences prior to actual execution on a superscalar [[microarchitecture]]; this opened up for dynamic scheduling of buffered ''partial'' instructions and enabled more parallelism to be extracted compared to the more rigid methods used in the simpler P5 Pentium; it also simplified [[speculative execution]] and allowed higher clock frequencies compared to designs such as the advanced [[Cyrix 6x86]].