Editing SuperH (section)

==History==
===SH-1 and SH-2===
[[Image:HD6417095 01.jpg|150px|thumb|SH-2 on Sega 32X and Sega Saturn]]
The SuperH processor core family was first developed by [[Hitachi]] in the early 1990s. The design concept was for a single [[instruction set]] (ISA) that would be [[upward compatible]] across a series of [[CPU core]]s.

In the past, this sort of design problem would have been solved using [[microcode]], with the low-end models in the series performing non-implemented instructions as a series of more basic instructions. For instance, a "long multiply" (multiplying two 32-bit registers to produce a 64-bit product) might be implemented in hardware on high-end models but instead be performed as a series of additions on low-end models.

One of the key realizations during the development of the [[RISC]] concept was that the microcode had a finite decoding time, and as processors became faster, this represented an unacceptable performance overhead. To address this, Hitachi instead developed a single ISA for the entire line, with unsupported instructions causing traps on those implementations that didn't include hardware support. For instance, the initial models in the line, the SH-1 and SH-2, differed only in their support for 64-bit multiplication; the SH-2 supported {{code|MUL}}, {{code|DMULS}} and {{code|DMULU}}, whereas the SH-1 would cause a trap if these were encountered.{{sfn|Program|1996|p=1}}

The SH-1 was the basic model, supporting a total of 56 instructions. The SH-2 added 64-bit multiplication and a few additional commands for branching and other duties, bringing the total to 62 supported instructions.{{sfn|Program|1996|p=1}} The SH-1 and the SH-2 were used in the [[Sega Saturn]], [[Sega 32X]] and [[Capcom CPS-3]].<ref>{{cite web |title=CP System III (CPS3) Hardware (Capcom) |url=https://www.system16.com/hardware.php?id=799 |website=www.system16.com |publisher=System 16 |access-date=3 August 2019}}</ref>

The ISA uses [[16-bit]] instructions for better code density than 32-bit instructions, which was important at the time due to the high cost of [[DRAM|main memory]] and the implementation cost of cache. As of 2023, code density is still important for small embedded systems and massively multicore processors. The downsides to this approach were that there were fewer bits available to encode a register number or a constant value. In the original SuperH ISA, there were only 16 general registers, requiring four bits for the source and another four for the destination; however some instructions have an implied R0, R15, or a system register as an extra operand. The instruction opcode is four, eight, twelve, or sixteen bits long, and the remaining four-bit fields are used for register or immediate operands in various ways: there are twelve classes of instructions, for a total of 142 instructions in SH-2.{{sfn|Program|1996|pp=30-33}}

Delayed branches are introduced for both SH-1 and SH-2. Unconditional branch instructions have one [[delay slot]].<ref>{{cite web |url=https://www.renesas.com/us/en/document/mah/superh-risc-engine-sh7020-and-sh7021-hd6437020-hd6477021-hd6437021-hd6417021?r=469371 |page=19,48 |title=SH7020 and SH7021 Hardware ManualSuperH™ RISC engine |accessdate=2023-12-02}}</ref>

===SH-3===
A few years later, the SH-3 core was added to the family; new features included another [[interrupt]] concept, a [[memory management unit]] (MMU), and a modified cache concept. These features required an extended instruction set, adding six new instructions for a total of 68.{{sfn|Program|1996|p=1}} The SH-3 was [[Endianness#Bi-endian hardware|bi-endian]], running in either big-endian or little-endian byte ordering.

The SH-3 core also added a [[digital signal processing|DSP]] extension, then called SH-3-DSP. With extended data paths for efficient DSP processing, special accumulators and a dedicated [[Multiply–accumulate|MAC]]-type DSP engine, this core unified the DSP and the RISC processor world. A derivative of the DSP was also used with the original SH-2 core.

Between 1994 and 1996, 35.1 million SuperH devices were shipped worldwide.<ref>{{cite web |url=http://segatech.com/technical/cpu/tech_sh4.html |archive-url=https://web.archive.org/web/20160305103423/http://segatech.com/technical/cpu/tech_sh4.html |archive-date=5 March 2016 |title=360-MIPS SuperH RISC Processor Enables Personal Access Systems SH7750 Launches the SH-4 Series |date = November 1997 }}</ref>

===SH-4===
In 1997, Hitachi and [[STMicroelectronics]] (STM) started collaborating on the design of the SH-4 for the [[Dreamcast]]. SH-4 featured [[superscalar]] (2-way) instruction execution and a [[vector processor|vector]] [[floating-point unit]] (particularly suited to [[3D graphics]]). Standard chips based on the SH-4 were introduced around 1998.<ref name=sh5/>

===Licensing===
In early 2001, Hitachi and STM formed the [[patent holding company|IP company]] SuperH, Inc., which was going to license the SH-4 core to other companies and was developing the SH-5 architecture, the first move of SuperH into the 64-bit area. The earlier SH-1 through 3 remained the property of Hitachi.<ref name=sh5>{{cite web |title=STMicro, Hitachi plan new company to develop RISC cores|url=http://www.eetimes.com/document.asp?doc_id=1180485 |date=3 April 2001 |website=EE Times|quote=Hitachi created the SH family of processors and developed its first four major iterations, but has worked with ST since 1997, when the companies agreed to share a common high-end microprocessor road map. They jointly developed the 32-bit SH4 RISC processor core, and began development of the SH5 architecture, which will now be completed by SuperH. SuperH's initial product will be the SH4 core. Earlier SH versions will not be part of the spin-off agreement.}}</ref><ref>{{cite web|title=SuperH, Inc. formed by Hitachi and STMicroelectronics to Boost the Proliferation of SuperH Cores in Embedded Microprocessor Applications|url=http://investors.st.com/phoenix.zhtml?c=111941&p=irol-newsArticle_print&ID=1454682|archive-url=https://archive.today/20160219085937/http://investors.st.com/phoenix.zhtml?c=111941&p=irol-newsArticle_print&ID=1454682|url-status=dead|archive-date=February 19, 2016}}</ref>

In 2003, Hitachi and [[Mitsubishi Electric]] formed a joint-venture called [[Renesas Electronics|Renesas Technology]], with Hitachi controlling 55% of it. In 2004, Renesas Technology bought STMicroelectronics's share of ownership in the SuperH Inc. and with it the licence to the SH cores.<ref>{{cite web|url=https://www.eetimes.com/renesas-to-take-over-superh-core-business/|date=28 September 2004|website=EE Times|title=Renesas to take over SuperH core business |first=Peter |last=Clarke}}</ref> Renesas Technology later became Renesas Electronics, following their merger with [[NEC Electronics]].

The SH-5 design supported two modes of operation: SHcompact mode, which is equivalent to the user-mode instructions of the SH-4 instruction set; and SHmedia mode, which is very different in that it uses 32-bit instructions with sixty-four 64-bit integer registers and [[Single instruction, multiple data|SIMD]] instructions. In SHmedia mode the destination of a [[branch (computer science)|branch]] (jump) is loaded into a branch register separately from the actual branch instruction. This allows the processor to prefetch instructions for a branch without having to snoop the instruction stream. The combination of a compact 16-bit instruction encoding with a more powerful 32-bit instruction encoding is not unique to SH-5; [[ARM architecture|ARM]] processors have a 16-bit [[ARM architecture#Thumb|Thumb]] mode (ARM licensed several patents from SuperH for Thumb<ref name="lwn"/>) and [[MIPS architecture|MIPS]] processors have a MIPS-16 mode. However, SH-5 differs because its backward compatibility mode is the 16-bit encoding rather than the 32-bit encoding.

The last evolutionary step happened around 2003 where the cores from SH-2 up to SH-4 were getting unified into a superscalar SH-X core which formed a kind of instruction set superset of the previous architectures, and added support for [[symmetric multiprocessing]].

===Continued availability===
Since 2010, the SuperH CPU cores, architecture and products are with [[Renesas Electronics]] and the architecture is consolidated around the SH-2, SH-2A, SH-3, SH-4 and SH-4A platforms. The system-on-chip products based on SH-3, SH-4 and SH-4A microprocessors were subsequently replaced by newer generations based on licensed CPU cores from [[Arm Ltd.]], with many of the existing models still marketed and sold until March 2025 through the Renesas Product Longevity Program.<ref>{{cite web|url=https://www.renesas.com/us/en/products/microcontrollers-microprocessors/other-mcus-mpus/superh-risc-engine-family-mcus|website=Renesas Electronics|title="SuperH RISC Engine Family MCUs"}}</ref>

As of 2021, the SH72xx microcontrollers based on the SH-2A continue to be marketed by Renesas with guaranteed availability until February 2029, along with newer products based on several other architectures including [[Arm architecture|Arm]], [[RX microcontroller family|RX]], and [[V850|RH850]].

===J Core===
{{Distinguish|Samsung Galaxy J2 Core}}
The last of the SH-2 patents expired in 2014. At [[LinuxCon]] Japan 2015, j-core developers presented a [[clean room design|cleanroom reimplemention]] of the SH-2 ISA with extensions (known as the "J2 core" due to the unexpired [[trademarks]]).<ref name="lwn">{{cite web|url=http://lwn.net/Articles/647636|title=Resurrecting the SuperH architecture|author=Nathan Willis|date=June 10, 2015|publisher=[[LWN.net]]}}</ref><ref name="0pf_jcore">{{cite web|url=http://j-core.org|title=J Cores|publisher=j-core|access-date=April 27, 2016|url-status=dead|archive-url=https://web.archive.org/web/20160511092659/http://j-core.org/|archive-date=May 11, 2016}}</ref> Subsequently, a design walkthrough was presented at ELC 2016.<ref>{{cite web |url=http://j-core.org/talks/ELC-2016.pdf |archive-url=https://web.archive.org/web/20160617085346/http://j-core.org/talks/ELC-2016.pdf |archive-date=2016-06-17 |url-status=live |title=j-core Design Walkthrough}}</ref>

The [[open-source license|open source]] [[Berkeley Software Distribution|BSD]]-licensed [[VHDL]] code for the J2 core has been proven on [[Xilinx]] [[FPGA]]s and on [[ASIC]]s manufactured on [[TSMC]]'s [[180 nm]] process, and is capable of booting [[μClinux]].<ref name="lwn"/>  J2 is backwards ISA compatible with SH-2, implemented as a 5-stage pipeline with separate Instruction and Data memory interfaces, and a machine-generated Instruction Decoder supporting the densely packed and complex (relative to other RISC machines) ISA.  Additional instructions are easy to add.  J2 implements instructions for dynamic shift (using the SH-3 and later instruction patterns), extended atomic operations (used for threading primitives) and locking/interfaces for symmetric multiprocessor support.  Plans to implement the SH-2A (as "J2+") and SH-4 (as "J4") instruction sets as the relevant patents expire<!--expired?--> in 2016–2017.<ref name="lwn"/>{{needs update|date=June 2022}}

Several features of SuperH have been cited as motivations for designing new cores based on this architecture:<ref name="lwn"/>

* High [[code density]] compared to other 32-bit [[RISC]] [[instruction set architecture|ISA]]s such as [[ARM architecture|ARM]] or [[MIPS architecture|MIPS]]<ref name="weaver2015">{{cite news|author=V.M. Weaver|title=Exploring the Limits of Code Density (Tech Report with Newest Results)|date=17 March 2015|url=http://web.eece.maine.edu/~vweaver/papers/iccd09/ll_document.pdf |archive-url=https://web.archive.org/web/20150713143728/http://web.eece.maine.edu/~vweaver/papers/iccd09/ll_document.pdf |archive-date=2015-07-13 |url-status=live}}</ref> important for cache and memory bandwidth performance
* Existing [[C compiler|compiler]] and [[operating system]] support ([[Linux]], [[Windows Embedded]], [[QNX]]<ref name="0pf_jcore"/>)
* Extremely low ASIC [[semiconductor fabrication|fabrication]] costs now that the patents are expiring (around {{USD|0.03}} for a dual-core J2 core on TSMC's 180&nbsp;nm process).
* Patent- and royalty-free (BSD-licensed) implementation
* Full and vibrant community support
* Availability of low cost hardware development platform for zero cost FPGA tools
* CPU and SoC RTL generation and integration tools, producing FPGA and ASIC portable RTL and documentation
* Clean, modern design with open source design, generation, simulation and verification environment