Editing Sequential logic (section)

== Synchronous sequential logic ==
Nearly all sequential logic today is ''clocked'' or ''synchronous'' logic. In a synchronous circuit, an [[electronic oscillator]] called a ''clock'' (or [[clock generator]]) generates a sequence of repetitive pulses called the ''[[clock signal]]'' which is distributed to all the memory elements in the circuit. The basic memory element in synchronous logic is the [[flip-flop (electronics)|flip-flop]]. The output of each flip-flop only changes when triggered by the clock pulse, so changes to the logic signals throughout the circuit all begin at the same time, at regular intervals, synchronized by the clock. 
      
The output of all the storage elements (flip-flops) in the circuit at any given time, the binary data they contain, is called the ''[[state (computer science)|state]]'' of the circuit. The state of the synchronous circuit only changes on clock pulses.  At each cycle, the next state is determined by the current state and the value of the input signals when the clock pulse occurs.

The main advantage of synchronous logic is its simplicity. The logic gates which perform the operations on the data require a finite amount of time to respond to changes to their inputs. This is called ''[[propagation delay]]''. The interval between clock pulses must be long enough so that all the logic gates have time to respond to the changes and their outputs "settle" to stable logic values before the next clock pulse occurs. As long as this condition is met (ignoring certain other details) the circuit is guaranteed to be stable and reliable. This determines the maximum operating speed of the synchronous circuit.

Synchronous logic has two main disadvantages:

* The maximum possible clock rate is determined by the slowest logic path in the circuit, otherwise known as the critical path. Every logical calculation, from the simplest to the most complex, must complete in one clock cycle. So logic paths that complete their calculations quickly are idle much of the time, waiting for the next clock pulse. Therefore, synchronous logic can be slower than asynchronous logic. One way to speed up synchronous circuits is to split complex operations into several simple operations which can be performed in successive clock cycles, a technique known as ''[[pipeline (computing)|pipelining]]''. This technique is extensively used in [[microprocessor]] design and helps to improve the performance of modern processors.
* The clock signal must be distributed to every flip-flop in the circuit. As the clock is usually a high-frequency signal, this distribution consumes a relatively large amount of power and dissipates much heat. Even the flip-flops that are doing nothing consume a small amount of power, thereby generating [[waste heat]] in the chip. In battery-powered devices, additional hardware and software complexity is required to reduce the clock speed or temporarily turn off the clock while the device is not being actively used, in order to maintain a usable battery life.