Editing SPARC (section)

==Features==
The SPARC architecture was heavily influenced by the earlier RISC designs, including the [[Berkeley RISC|RISC]] I and II from the [[University of California, Berkeley]] and the [[IBM 801]]. These original RISC designs were minimalist, including as few features or op-codes as possible and aiming to execute instructions at a rate of almost one instruction per [[clock signal|clock cycle]]. This made them similar to the [[MIPS architecture]] in many ways, including the lack of instructions such as multiply or divide. Another feature of SPARC influenced by this early RISC movement is the [[branch delay slot]].

The SPARC processor usually contains as many as 160 [[processor register|general-purpose registers]]. According to the "Oracle SPARC Architecture 2015" specification an "implementation may contain from 72 to 640 general-purpose 64-bit" registers.<ref name="SPARC 2015">{{cite web |url=https://www.oracle.com/technetwork/server-storage/sun-sparc-enterprise/documentation/sparc-architecture-2015-2868130.pdf |title=Oracle SPARC Architecture 2015: One Architecture ... Multiple Innovative Implementations |version=Draft D1.0.0 |date=January 12, 2016 |quote=<!--p.16-->IMPL. DEP. #2-V8: An Oracle SPARC Architecture implementation may contain from 72 to 640 general-purpose 64-bit R registers. This corresponds to a grouping of the registers into MAXPGL + 1 sets of global R registers plus a circular stack of N_REG_WINDOWS sets of 16 registers each, known as register windows. The number of register windows present (N_REG_WINDOWS) is implementation dependent, within the range of 3 to 32 (inclusive).<!--"Variants of load/store instructions, the load/store alternate instructions, can specify an arbitrary 8-bit address space identifier for the load/store data access."--><!--Possibly a "typo" for thirty-two 64-bit registers?: "The floating-point register set consists of sixty-four 32-bit registers, which may be accessed as follows:"--> |access-date=June 13, 2016 |archive-date=April 24, 2016 |archive-url=https://web.archive.org/web/20160424051826/http://www.oracle.com/technetwork/server-storage/sun-sparc-enterprise/documentation/sparc-architecture-2015-2868130.pdf |url-status=live }}</ref> At any point, only 32 of them are immediately visible to software&nbsp;— 8 are a set of global registers (one of which, '''g0''', is hard-wired to zero, so only seven of them are usable as registers) and the other 24 are from the [[stack (abstract data type)|stack]] of registers. These 24 registers form what is called a [[register window]], and at function call/return, this window is moved up and down the register stack. Each window has eight local registers and shares eight registers with each of the adjacent windows. The shared registers are used for passing function parameters and returning values, and the local registers are used for retaining local values across function calls.

The "scalable" in SPARC comes from the fact that the SPARC specification allows implementations to scale from embedded processors up through large server processors, all sharing the same core (non-privileged) instruction set.  One of the architectural parameters that can scale is the number of implemented register windows; the specification allows from three to 32 windows to be implemented, so the implementation can choose to implement all 32 to provide maximum [[call stack]] efficiency, or to implement only three to reduce cost and complexity of the design, or to implement some number between them. Other architectures that include similar [[register file]] features include [[Intel i960]], [[IA-64]], and [[AMD 29000]].

The architecture has gone through several revisions. It gained hardware multiply and divide functionality in version 8.{{R|gcc-doc|osnews-gcc}} [[64-bit computing|64-bit]] (addressing and data) were added to the version 9 SPARC specification published in 1994.<ref name="sparc-v9-whitepaper" />

In SPARC version 8, the [[floating-point arithmetic|floating-point]] register file has 16 [[double-precision floating-point format|double-precision]] registers. Each of them can be used as two [[single-precision floating-point format|single-precision]] registers, providing a total of 32 single-precision registers. An odd–even number pair of double-precision registers can be used as a [[quadruple-precision floating-point format|quad-precision]] register, thus allowing 8 quad-precision registers. SPARC Version 9 added 16 more double-precision registers (which can also be accessed as 8 quad-precision registers), but these additional registers can not be accessed as single-precision registers. No SPARC CPU implements quad-precision operations in hardware as of 2024.<ref>{{Cite book
| title = Numerical Computation Guide – Sun Studio 10
| chapter = SPARC Behavior and Implementation
| year = 2004
| publisher = Sun Microsystems, Inc
| chapter-url = https://download.oracle.com/docs/cd/E19059-01/stud.10/819-0499/ncg_sparc.html
| access-date = September 24, 2011
| quote = There are four situations, however, when the hardware will not successfully complete a floating-point instruction: ...&nbsp;The instruction is not implemented by the hardware (such as&nbsp;... quad-precision instructions on any SPARC FPU).
| archive-date = January 25, 2022
| archive-url = https://web.archive.org/web/20220125121541/https://docs.oracle.com/cd/E19059-01/stud.10/819-0499/ncg_sparc.html
| url-status = live
}}</ref>

[[Tagged architecture|Tagged]] add and subtract instructions perform adds and subtracts on values checking that the bottom two bits of both operands are 0 and reporting overflow if they are not.  This can be useful in the implementation of the [[run-time system|run time]] for [[ML (programming language)|ML]], [[Lisp (programming language)|Lisp]], and similar languages that might use a tagged integer format.

The [[endianness]] of the [[32-bit computing|32-bit]] SPARC V8 architecture is purely big-endian. The 64-bit SPARC V9 architecture uses big-endian instructions, but can access data in either big-endian or little-endian byte order, chosen either at the application instruction ([[load–store unit|load–store]]) level or at the [[paging|memory page]] level (via an MMU setting).  The latter is often used for accessing data from inherently little-endian devices, such as those on PCI buses.