Editing S-100 bus (section)

==Architecture==
The {{nowrap|S-100}} bus is a [[passive backplane]] of 100-pin printed circuit board edge connectors wired in parallel. Circuit cards measuring {{cvt|5|x|10|in|cm}} serving the functions of CPU, memory, or I/O interface plugged into these connectors. The bus signal definitions closely follow those of an 8080 microprocessor system, since the [[Intel 8080]] microprocessor was the first microprocessor hosted on the {{nowrap|S-100}} bus. The 100 lines of the {{nowrap|S-100}} bus can be grouped into four types: 1) Power, 2) Data, 3) Address, and 4) Clock and control.<ref name=Garland>{{cite book|last=Garland|first=Harry|title=Introduction to Microprocessor System Design|year=1979|pages=[https://archive.org/details/introductiontomi00garl/page/159 159–169]|quote=Although many other processors have been adapted to the {{nowrap|S-100}} bus, the bus signal definitions closely follow those of an 8080 system.|publisher=McGraw-Hill|location=New York |isbn=0-07-022871-X |url-access=registration|url=https://archive.org/details/introductiontomi00garl/page/159}}</ref>

Power supplied on the bus is bulk unregulated +8 Volt DC and ±16 Volt DC, designed to be [[Voltage regulator|regulated]] on the cards to +5 V (used by [[Transistor-transistor logic|TTL]] ICs), -5 V and +12 V for the [[Intel 8080]] CPU IC, ±12 V  [[RS-232]] line driver ICs, +12 V for disk drive motors. The onboard voltage regulation is typically performed by devices of the [[78xx]] family (for example, a 7805 device to produce +5 volts). These are [[linear regulator]]s which are commonly mounted on heat sinks.

The bi-directional 8-bit data bus of the Intel 8080 is split into two unidirectional 8-bit data buses. The processor could use only one of these at a time. The [[Sol-20]] used a variation that had only a single 8-bit bus and used the now-unused pins as signal grounds to reduce [[electronic noise]]. The direction of the bus, in or out, was signaled using the otherwise unused DBIN pin. This became universal in the {{nowrap|S-100}} market as well, making the second bus superfluous. Later, these two 8-bit buses would be combined to support a 16-bit data width for more advanced processors, using the Sol's system to signal the direction.

The address bus is 16-bits wide in the initial implementation and later extended to 24-bits wide. A bus control signal can put these lines in a [[Three-state logic|tri-state]] condition to allow direct memory access. The [[Cromemco Dazzler]], for example, is an early {{nowrap|S-100}} card that retrieved digital images from memory using direct memory access.

Clock and control signals are used to manage the traffic on the bus. For example, the ''DO Disable'' line will tristate the address lines during direct memory access. Unassigned lines of the original bus specification were later assigned to support more advanced processors. For example, the [[Zilog]] [[Zilog Z80|Z-80]] processor has a [[non-maskable interrupt]] line that the Intel 8080 processor does not. One unassigned line of the {{nowrap|S-100}} bus then was reassigned to support the non-maskable interrupt request.