Editing PA-RISC (section)

==History==
In the late 1980s, HP was building four series of computers, all based on [[Complex instruction set computer|CISC]] CPUs. One line was the [[IBM PC compatible]] Intel [[i286]]-based Vectra Series, started in 1986. All others were non-[[Intel]] systems. One of them was the HP Series 300 of [[Motorola 68000]]-based [[workstation]]s, another Series 200 line of technical workstations based on a custom [[silicon on sapphire]] (SOS) chip design, the SOS based 16-bit [[HP 3000]] classic series, and finally the HP 9000 Series 500 [[minicomputer]]s, based on their own (16- and 32-bit) [[HP FOCUS|FOCUS]] microprocessor.

The Precision Architecture is the result of what was known inside Hewlett-Packard as the '''Spectrum''' program.<ref>{{cite journal |url=http://www.hpl.hp.com/hpjournal/pdfs/IssuePDFs/1986-08.pdf |first=William S. |last=Worley |title= Hewlett-Packard Precision Architecture: The Processor |journal=Hewlett-Packard Journal |date=August 1986 |volume=37 |issue=8 |pages=4–22 |quote=The HP Precision Architecture development program, known within HP as the Spectrum program, ...}}</ref> HP planned to use Spectrum to move all of their non-PC compatible machines to a single RISC CPU family.

In early 1982, work on the Precision Architecture began at HP Laboratories, defining the instruction set and virtual memory system. Development of the first [[transistor–transistor logic|TTL]] implementation started in April 1983. With simulation of the processor having completed in 1983, a final processor design was delivered to software developers in July 1984. Systems prototyping followed, with "lab prototypes" being produced in 1985 and product prototypes in 1986.<ref name="fotland198703">{{ cite journal | url=https://archive.org/details/Hewlett-Packard_Journal_Vol._38_No._3_1987-03_Hewlett-Packard/page/n3/mode/2up | title=Hardware Design of the First HP Precision Architecture Computers | last1=Fotland | first1=David A. | last2=Shelton | first2=John F. | last3=Bryg | first3=William R. | last4=La Fetra | first4=Ross V. | last5=Boschma | first5=Simin I. | last6=Yeh | first6=Allan S. | last7=Jacobs | first7=Edward M. | journal=Hewlett-Packard Journal | date=March 1987 | access-date=6 October 2020 | volume=38 | issue=3 | pages=4–17 }}</ref>

The first processors were introduced in products during 1986. It has thirty-two 32-bit integer registers and sixteen 64-bit floating-point registers.  The HP Precision Architecture has a single [[branch delay slot]]. This means that the instruction immediately following a branch instruction is executed before the program's control flow is transferred to the target instruction of the branch.<ref>{{cite web |url=https://www.hpl.hp.com/hpjournal/pdfs/IssuePDFs/1986-08.pdf |page=10 |title=Hewlett-Packard Precision Architecture: The Processor |accessdate=2023-12-02}}</ref><ref>{{Cite conference |url=https://dl.acm.org/doi/pdf/10.1145/30350.30352 |first1=John A. |last1=DeRosa |first2=Henry M. |last2=Levy |title=An Evaluation of Branch Architectures |book-title=Proceedings of the 14th annual international symposium on Computer architecture |pages=10–16 |date=1987 |doi=10.1145/30350.30352 |isbn=0-8186-0776-9 |accessdate=2024-01-27}}</ref> An HP Precision processor also includes a Processor Status Word (PSW) register. The PSW register contains various flags that enable virtual addressing, protection, [[interrupt]]ions, and other status information.<ref>{{cite web |url=https://www.hpl.hp.com/hpjournal/pdfs/IssuePDFs/1986-08.pdf |page=6 |title=Hewlett-Packard Precision Architecture: The Processor |accessdate=2023-12-07}}</ref> The number of floating-point registers was doubled in the 1.1 version to 32 once it became apparent that 16 were inadequate and restricted performance. The architects included Allen Baum, Hans Jeans, Michael J. Mahon, [[Ruby B. Lee|Ruby Bei-Loh Lee]], Russel Kao, [[Steve Muchnick]], Terrence C. Miller, David Fotland, and William S. Worley.<ref>Smotherman, Mark (2 July 2009). [http://www.cs.clemson.edu/~mark/architects.html ''Recent Processor Architects''] {{Webarchive|url=https://web.archive.org/web/20120910143451/http://www.cs.clemson.edu/~mark/architects.html |date=10 September 2012 }}.</ref>

The first implementation was the TS1, a central processing unit built from discrete [[transistor–transistor logic]] ([[74F TTL]]) devices. Later implementations were multi-chip VLSI designs fabricated in NMOS processes (NS1 and NS2) and CMOS (CS1 and PCX).<ref>Paul Weissmann.
[http://www.openpa.net/systems/hp_early-systems.html "Early PA-RISC Systems"] {{Webarchive|url=https://web.archive.org/web/20141002195056/http://www.openpa.net/systems/hp_early-systems.html |date=2 October 2014 }}.</ref>
They were first used in a new series of [[HP 3000]] machines in the late 1980s&nbsp;– the 930 and 950, commonly known at the time as Spectrum systems, the name given to them in the development labs. These machines ran [[HP Multi-Programming Executive|MPE-XL]]. The [[HP 9000]] machines were soon upgraded with the PA-RISC processor as well, running the [[HP-UX]] version of [[Unix]].

Other operating systems ported to the PA-RISC architecture include [[Linux]], [[OpenBSD]], [[NetBSD]], [[OSF/1]], [[NeXTSTEP]], and [[ChorusOS]].<ref>{{Cite report |title=Porting Chorus to the PA-RISC: Project Overview |date=January 1992 |url=https://pdxscholar.library.pdx.edu/cgi/viewcontent.cgi?article=1059&context=compsci_fac |last1=Walpole |first1=Jonathan |url-status=live |last2=Hakanson |first2=Marion |publisher=Oregon Graduate Institute Of Science And Technology |last3=Inouye |first3=Jon |last4=Konuru |first4=Ravi |archive-url=https://web.archive.org/web/20230612184225/https://pdxscholar.library.pdx.edu/cgi/viewcontent.cgi?article=1059&context=compsci_fac |format=PDF |archive-date=12 June 2023}}</ref>

An interesting aspect of the PA-RISC line is that most of its generations have no level 2 [[CPU cache|cache]]. Instead large level 1 caches are used, initially as separate chips connected by a bus, and later integrated on-chip. Only the PA-7100LC and PA-7300LC have L2 caches. Another innovation of the PA-RISC is the addition of vector instructions ([[Single instruction, multiple data|SIMD]]) in the form of [[Multimedia Acceleration eXtensions|MAX]], which were first introduced on the PA-7100LC.

'''Precision RISC Organization''', an industry group led by HP, was founded in 1992, to promote the PA-RISC architecture.  Members included [[Convex Computer|Convex]], [[Hitachi]], [[Hughes Aircraft Company|Hughes Aircraft]], [[Mitsubishi Electric|Mitsubishi]], [[NEC]], [[Oki Electric Industry|OKI]], [[Prime Computer|Prime]], [[Stratus Technologies|Stratus]], [[Yokogawa Electric|Yokogawa]], [[Red Brick Software]], and [[Allegro Consultants, Inc.]]

The ISA was extended in 1996 to 64&nbsp;bits, with this revision named PA-RISC 2.0. PA-RISC 2.0 also added [[fused multiply–add]] instructions, which help certain floating-point intensive algorithms, and the [[Multimedia Acceleration eXtensions|MAX-2]] SIMD extension, which provides instructions for accelerating multimedia applications. The first PA-RISC 2.0 implementation was the [[PA-8000]], which was introduced in January 1996.