Editing Opteron (section)

==Technical description==
[[File:AMD Opteron 2212 IMGP1795.jpg|thumb|Opteron 2212]]
[[File:OS6132VAT8EGO.jpg|thumb|Back of "Magny-Cours" processor (OS6132VAT8EGO)]]

===Key capabilities===
Opteron combines two important capabilities in a single processor:
# native execution of legacy x86 [[32-bit]] applications without speed penalties
# native execution of x86-64 [[64-bit]] applications

The first capability is notable because at the time of Opteron's introduction, the only other [[64-bit]] architecture marketed with [[32-bit]] [[x86]] compatibility (Intel's [[Itanium]]) ran [[x86]] legacy-applications only with significant speed degradation. The second capability, by itself, is less noteworthy, as major [[RISC]] architectures (such as [[SPARC]], [[DEC Alpha|Alpha]], [[PA-RISC]], [[PowerPC]], [[MIPS architecture|MIPS]]) have been 64-bit for many years.  In combining these two capabilities, however, the Opteron earned recognition for its ability to run the vast installed base of x86 applications economically, while simultaneously offering an upgrade path to [[64-bit computing]].

The Opteron processor possesses an integrated [[memory controller]] supporting [[DDR SDRAM]], [[DDR2 SDRAM]] or [[DDR3 SDRAM]] (depending on processor generation).  This both reduces the latency penalty for accessing the main [[Random-access memory|RAM]] and eliminates the need for a separate [[northbridge (computing)|northbridge]] chip.

===Multi-processor features===
In multi-processor systems (more than one Opteron on a single [[motherboard]]), the [[Central processing unit|CPUs]] communicate using the [[Direct Connect Architecture]] over high-speed [[HyperTransport]] links. Each CPU can access the main memory of another processor, transparent to the programmer. The Opteron approach to multi-processing is not the same as standard [[symmetric multiprocessing]]; instead of having one bank of memory for all CPUs, each CPU has its own memory. Thus the Opteron is a [[Non-Uniform Memory Access]] (NUMA) architecture. The Opteron CPU directly supports up to an 8-way configuration, which can be found in mid-level servers. Enterprise-level servers use additional (and expensive) routing chips to support more than 8 CPUs per box.

In a variety of computing benchmarks, the Opteron architecture has demonstrated better multi-processor scaling than the Intel [[Xeon]]<ref>{{cite web | title=SPECint2006 Rate Results for multiprocessor systems | url=http://www.spec.org/cgi-bin/osgresults | access-date = December 27, 2008 }}</ref> which did not have a point to point system until QPI and integrated memory controllers with the Nehalem design. This is primarily because adding another Opteron processor increases memory bandwidth, while that is not always the case for Xeon systems, and the fact that the Opterons use a [[switched fabric]], rather than a shared [[bus (computing)|bus]]. In particular, the Opteron's integrated memory controller allows the CPU to access local [[Random-access memory|RAM]] very quickly.  In contrast, multiprocessor Xeon system CPUs share only two common buses for both processor-processor and processor-memory communication. As the number of CPUs increases in a typical Xeon system, [[bus contention|contention]] for the shared bus causes computing efficiency to drop. Intel migrated to a memory architecture similar to the Opteron's for the [[Intel Core i7]] family of processors and their Xeon derivatives.

===Multi-core Opterons===
[[File:Quad-Core AMD Opteron processor.jpg|thumb|Quad-core "Barcelona" Opteron]]
[[File:AMD Opteron Six Cores.jpg|thumb|Six-core "Istanbul" Opteron]]
In April 2005, AMD introduced its first multi-core Opterons. At the time, AMD's use of the term multi-core in practice meant [[dual-core]]; each physical Opteron chip contained two processor cores. This effectively doubled the computing performance available to each motherboard processor socket. One socket could then deliver the performance of two processors, two sockets could deliver the performance of four processors, and so on. Because motherboard costs increase dramatically as the number of CPU sockets increase, multicore CPUs enable a multiprocessing system to be built at lower cost.

AMD's model number scheme has changed somewhat in light of its new multicore lineup. At the time of its introduction, AMD's fastest multicore Opteron was the model 875, with two cores running at 2.2 [[GHz]] each. AMD's fastest single-core Opteron at this time was the model 252, with one core running at 2.6&nbsp;GHz. For [[Multithreading (computer architecture)|multithreaded]] applications, or many single threaded applications, the model 875 would be much faster than the model 252.

Second-generation Opterons are offered in three series: the 1000 Series (single socket only), the 2000 Series (dual socket-capable), and the 8000 Series (quad or octo socket-capable). The 1000 Series uses the [[Socket AM2|AM2 socket]]. The 2000 Series and 8000 Series use [[Socket F]].[https://www.amd.com/us-en/Processors/ProductInformation/0,,30_118_8796_14309,00.html]

AMD announced its third-generation [[quad-core]] Opteron chips on September 10, 2007<ref>{{Cite news |title= AMD Introduces the World's Most Advanced x86 Processor, Designed for the Demanding Datacenter
|work= Press release |date= September 10, 2007 |publisher= AMD |url= https://www.amd.com/us/press-releases/Pages/Press_Release_119768.aspx |access-date= January 6, 2014 }}</ref><ref>{{Cite web |title= The Inner circuitry of the powerful quad-core AMD processor |publisher= AMD |work= Photo |url= https://www.amd.com/us-en/assets/content_type/Additional/DieImageGallert.swf |url-status= dead |archive-url= https://web.archive.org/web/20081128075230/http://www.amd.com/us-en/assets/content_type/Additional/DieImageGallert.swf |archive-date= November 28, 2008 |access-date= January 6, 2011 }}</ref> 
with hardware vendors announcing servers in the following month. Based on a core design codenamed ''Barcelona'', new power and thermal management techniques were planned for the chips. Earlier dual core DDR2 based platforms were upgradeable to quad core chips.<ref>{{cite web
  | title = Quad-Core Upgradeability
  | url = https://www.amd.com/us-en/Processors/ProductInformation/0,,30_118_8796_14286,00.html
  | access-date = March 6, 2007 }}
6-core Opteron Processors codenamed 'Istanbul' were announced on July 1, 2009. They were a drop-in upgrade for existing Socket F servers.
</ref>
The fourth generation was announced in June 2009 with the ''Istanbul'' hexa-cores. It introduced ''HT&nbsp;Assist'', an additional directory for data location, reducing the overhead for probing and broadcasts. HT&nbsp;Assist uses 1 MB L3 cache per CPU when activated.<ref>{{cite web
  | title = "HT Assist": What is it, and how does it help?
  | url = https://www.amd.com/us/products/server/processors/six-core-opteron/Pages/six-core-faq-ht-assist.aspx
  | access-date = January 2, 2013}}</ref>

In March 2010 AMD released the ''Magny-Cours'' Opteron 6100 series CPUs for [[Socket G34]]. These are 8- and 12-core [[multi-chip module]] CPUs consisting of two four or six-core dies with a [[HyperTransport]] 3.1 link connecting the two dies. These CPUs updated the multi-socket Opteron platform to use DDR3 memory and increased the maximum HyperTransport link speed from 2.40&nbsp;GHz (4.80&nbsp;GT/s) for the ''Istanbul'' CPUs to 3.20&nbsp;GHz (6.40&nbsp;GT/s).

AMD changed the naming scheme for its Opteron models. Opteron 4000 series CPUs on Socket C32 (released July 2010) are dual-socket capable and are targeted at uniprocessor and dual-processor uses. The Opteron 6000 series CPUs on Socket G34 are quad-socket capable and are targeted at high-end dual-processor and quad-processor applications.

=== CPU socket models ===

==== Socket 939 ====
AMD released [[Socket 939]] Opterons, reducing the cost of motherboards for low-end servers and workstations. Except for the fact they have 1&nbsp;[[megabyte|MB]] L2 cache (versus 512&nbsp;[[kilobyte|KB]] for the Athlon 64) the Socket 939 Opterons are identical to the San Diego and Toledo core [[Athlon 64]]s, but are run at lower clock speeds than the cores are capable of, making them more stable.

==== Socket AM2 ====
Socket AM2 Opterons are available for servers that only have a single-chip setup. Codenamed Santa Ana, rev. F dual core AM2 Opterons feature 2 × 1&nbsp;MB L2 cache, unlike the majority of their [[Athlon 64 X2]] cousins which feature 2 × 512&nbsp;KB L2 cache. These CPUs are given model numbers ranging from 1210 to 1224.

==== Socket AM2+ ====
AMD introduced three quad-core Opterons on Socket AM2+ for single-CPU servers in 2007. These CPUs are produced on a 65&nbsp;nm manufacturing process and are similar to the ''Agena'' [[AMD Phenom|Phenom]] X4 CPUs. The Socket AM2+ quad-core Opterons are code-named "Budapest". The Socket AM2+ Opterons carry model numbers of 1352 (2.10&nbsp;GHz), 1354 (2.20&nbsp;GHz), and 1356 (2.30&nbsp;GHz).

==== Socket AM3 ====
AMD introduced three quad-core Opterons on Socket AM3 for single-CPU servers in 2009. These CPUs are produced on a 45&nbsp;nm manufacturing process and are similar to the ''Deneb''-based Phenom II X4 CPUs. The Socket AM3 quad-core Opterons are code-named "Suzuka". These CPUs carry model numbers of 1381 (2.50&nbsp;GHz), 1385 (2.70&nbsp;GHz), and 1389 (2.90&nbsp;GHz).

==== Socket AM3+ ====
[[Socket AM3+]] was introduced in 2011 and is a modification of AM3 for the [[Bulldozer (processor)|Bulldozer]] microarchitecture. Opteron CPUs in the AM3+ package are named Opteron 3xxx.

==== Socket F ====
[[Socket F]] ([[land grid array|LGA]] 1207 contacts) is AMD’s second generation of Opteron socket. This socket supports processors such as the Santa Rosa, Barcelona, Shanghai, and Istanbul codenamed processors. the "lidded [[land grid array]]" socket adds support for [[DDR2 SDRAM]] and improved [[HyperTransport]] version 3 connectivity. Physically the socket and processor package are nearly identical, although not generally compatible with [[socket 1207 FX]].

==== Socket G34 ====
[[Socket G34]] (LGA 1944 contacts) is one of the third generation of Opteron sockets, along with [[Socket C32]]. This socket supports ''Magny-Cours'' Opteron 6100, Bulldozer-based ''Interlagos'' Opteron 6200, and Piledriver-based "Abu Dhabi" Opteron 6300 series processors. This socket supports four channels of [[DDR3 SDRAM]] (two per CPU die). Unlike previous multi-CPU Opteron sockets, Socket G34 CPUs will function with unbuffered ECC or non-ECC RAM in addition to the traditional registered ECC RAM.

==== Socket C32 ====
[[Socket C32]] (LGA 1207 contacts) is the other member of the third generation of Opteron sockets. This socket is physically similar to [[Socket F]] but is not compatible with Socket F CPUs. Socket C32 uses DDR3 SDRAM and is keyed differently so as to prevent the insertion of Socket F CPUs that can use only DDR2 SDRAM. Like Socket G34, Socket C32 CPUs will be able to use unbuffered ECC or non-ECC RAM in addition to registered ECC SDRAM.

===== Micro-architecture update =====
The Opteron line saw an update with the implementation of the [[AMD K10]] microarchitecture. New processors, launched in the third quarter of 2007 (codename ''Barcelona''), incorporate a variety of improvements, particularly in memory prefetching, speculative loads, [[SIMD]] execution and [[branch predictor|branch prediction]], yielding an appreciable performance improvement over K8-based Opterons, within the same power envelope.<ref>{{cite news |last=Merritt |first=Rick |title=AMD tips quad-core performance |url=http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=197700269 |publisher=EETimes.com |access-date=March 16, 2007}}</ref>

In 2007 AMD introduced a scheme to characterize the power consumption of new processors under "average" daily usage, named [[average CPU power]] (ACP).

==== Socket FT3 ====
The Opteron X1150 and Opteron X2150 APU are used with the BGA-769 or [[Socket FT3]].<ref>{{cite web |title=AMD Opteron X2150 APU |url=https://www.amd.com/en-us/products/server/opteron-x/x2150#specs |access-date=October 19, 2014}}</ref>