Editing NS32000 (section)

==Design concept==
[[File:Kl National Semiconductor NS32008.jpg|thumb|NS32008 microprocessor]]

The NS32000 series traces its history to an effort by National Semiconductor to produce a single-chip implementation of the [[VAX-11]] architecture.<ref name="tilson198310">{{cite magazine | url=https://archive.org/stream/byte-magazine-1983-10/1983_10_BYTE_08-10_UNIX#page/n267/mode/2up | title=Moving Unix to New Machines | magazine=BYTE | volume=8 | issue=10 | date=October 1983 | access-date=31 January 2015 | author=Tilson, Michael | pages=266–276}}</ref> The VAX is well known for its highly "orthogonal" [[instruction set architecture]] (ISA), in which any instruction can be applied to any data. For instance, an <code>ADD</code> instruction might add the contents of two [[processor register]]s, or one register against a value in memory, two values in memory, or use the register as an offset against an address. This flexibility was considered the paragon of design in the era of [[complex instruction set computer]]s (CISC).<ref name="leedy198304"/>

National took [[Digital Equipment Corporation]] (DEC) to court in [[California]] to ensure the legality of the design, but when DEC had the lawsuit moved to [[Massachusetts]], DEC's home state, the lawsuit was dropped and the Series 32000 architecture was developed instead. Although the new [[instruction set architecture]] was not VAX-11 compatible, it did retain its highly "[[orthogonal instruction set|orthogonal]]" design philosophy. That is, every instruction could be used with any type of data. Articles of the time also referred to this as "symmetrical".<ref name="leedy198304"/>

The original processor family consisted of the NS16032 CPU and a NS16C032 low-power variant, both having a 16-bit data path and so requiring two machine cycles to load a single 32-bit word. Both could be used with the NS16082 [[memory management unit]] (MMU), which provided 24-bit [[virtual memory]] support for up to 16&nbsp;MB physical memory. The NS16008 was a cut-down version with an 8-bit external data path and no virtual memory support, which had a reduced pin count and was thus somewhat easier to implement.<ref name="leedy198304"/> Both the NS16008 and NS16016 were to feature an emulation mode for the [[Intel 8080]] running at four times the speed of that processor.<ref name="interfaceage19811_advances">{{ cite magazine | url=https://archive.org/details/InterfaceAge198111/page/n95/mode/2up | title=Advances in CPU Design | magazine=Interface Age | last1=Cole | first1=Bernard Conrad | date=November 1981 | access-date=2 March 2023 | pages=94–97 }}</ref>

At the same time, National Semiconductor also announced two future versions, the NS32032 and NS32132. The former was essentially a version of the NS16032 with a 32-bit external data bus, allowing it to read data at twice the rate. This was project to be released in 1984. The NS32132 was a version with a 29-bit internal addresses and 32-bit external, allowing it to address a complete 4&nbsp;GB of memory. It was to be released in 1985.<ref name="leedy198304"/>

All of these could also be used with the NS16081 [[floating-point unit]] (FPU).<ref name="leedy198304" />