Editing Motorola 88000 (section)

== History ==
===Background===
Motorola entered the 1980s in a position of strength; the company's recently-introduced [[Motorola 68000]] easily outperformed any other microprocessor on the market, and its 32-bit architecture was naturally suited to the emerging [[workstation]] market. [[Intel]] was not moving aggressively into the 32-bit space, and the companies that did, notably [[National Semiconductor]], botched their releases and left Motorola in control of everything that was not [[Intel]]. At the time, Intel held about 80% of the overall computer market, while Motorola controlled 90% of the rest.

Into this came the early 1980's introduction of the RISC concept. At first, there was an intense debate within the industry whether the concept would actually improve performance, or if its longer [[machine language]] programs would actually slow the execution through additional memory accesses. All such debate was ended by the mid-1980s when the first RISC-based workstations emerged; the latest [[Sun-3|Sun-3/80]] running on a 20&nbsp;MHz [[Motorola 68030]] delivered about 3 MIPS, whereas the first [[SPARC]]-based [[Sun-4|Sun-4/260]] with a 16&nbsp;MHz [[SPARC]] delivered 10 MIPS. [[Hewlett-Packard]], [[Digital Equipment Corporation|DEC]] and other large vendors all began moving to RISC platforms.

This shift in the market had the potential to lock Motorola out of the workstation market, one of its only strongholds and among its most lucrative. Apple remained the company's only large vendor outside the workstation space; other users of the 68000, notably [[Atari Corporation]] and [[Commodore International]], were floundering in a market that was rapidly standardizing on [[IBM PC compatible]]s.<ref>{{cite web |url=https://arstechnica.com/features/2005/12/total-share/ |title=Total share: 30 years of personal computer market share figures |first=Jeremy |last=Reimer |website=Ars Technica|date=15 December 2005 }}</ref>

===Motorola's approach===
RISC designs were a conscious effort to tailor the processor to the types of operations being called by the [[compiler]]s on that platform, in the case of Unix workstations, the [[C programming language]]. The seminal [[IBM 801]] project had noted that compilers generally did not use the vast majority of the instructions available to them, and instead used the simplest version of the instructions, often because these performed the fastest. Yet the circuitry providing the other versions of these instructions added overhead even to the simplest version. Removing these unused instructions from the CPU eliminated this overhead and freed up significant room on the chip. This gave room to increase the number of [[processor register]]s, which had a far greater impact on performance than the removed special-case instructions. For this reason, the RISC concept can be said to be driven by the real-world design of compilers.{{sfn|Lid}}

Motorola's articles on the 88000 design speak of single-cycle instructions, large [[processor register]] files and other hallmarks of the RISC concept, but don't mention the word "RISC" even once.{{sfn|Alsup|1990}} As existing RISC designs had entered the market already, the company decided that it would not attempt to compete with these and would instead produce the world's most powerful processor. To do this, it took design notes from one of the fastest computers of a previous era, the [[CDC 6600]] [[supercomputer]]. In particular, it adopted the 6600's concept of a [[Scoreboarding|scoreboard]]. Scoreboarding allowed the CPU to examine the instruction's use of registers and immediately dispatch those that did not rely on previous calculations that were not yet complete; this allowed the instructions to be re-ordered to allow ones that had their required data to run while others had their data loaded from the cache or memory. This instruction reordering could improve usage by as much as 35%.{{sfn|Alsup|1990|p=51}}

The design also used separate data and instruction address buses. This was costly in terms of pin count; both the instruction and data caches had 32 pins for their address and 32 pins for the data, meaning the complete system used 128 pins on the "P-bus". This design was based on the observation that only about one-third of operations were memory-related; the rest were operating on data already read. This strongly favored having a dedicated instruction pathway to an external instruction cache. The caches and associated [[memory management unit]]s (MMU) were initially external, a cache controller could be connected to either the data or instruction buses, and up to four controllers could be used on either bus. Internally there were three 32-bit buses, connected to the internal units in different ways as required for reading and writing data to the registers.{{sfn|Alsup|1990|p=49}}

Another feature of the new design was its built-in support for specialized co-processors, or "special function units", or SFUs.{{sfn|Alsup|1990|p=49}} In addition to the internal commands supported out of the box, it set aside blocks of 256 instructions that could be used by co-processors. This was aimed at designers who wished to customize the system; new functional units could be added without affecting the existing [[instruction set architecture]], ensuring software compatibility for the main functionality.{{sfn|Lid}} Every 88000 came with SFU1 already installed, the [[floating point unit]] (FPU).{{sfn|Alsup|1990|p=49}} The branch and jump instructions incorporate a [[delay slot|delayed branch]] option (.n), which can be specified to ensure that the subsequent sequential instruction is executed before the branch target instruction, irrespective of the branch condition.<ref>{{Cite web |url=http://www.bitsavers.org/components/motorola/88000/MC88100_RISC_Microprocessor_Users_Manual_2ed_1990.pdf#page=81 |title=MC88100 RISC Microprocessor User's Manual |page=81(3-26) |accessdate=2023-12-21}}</ref> Placing branch instruction or other instruction which may change the instruction pointer, in the branch delay slot is deprecated to maintain future compatibility.<ref>{{Cite web |url=http://www.bitsavers.org/components/motorola/88000/MC88100_RISC_Microprocessor_Users_Manual_2ed_1990.pdf#page=88 |title=MC88100 RISC Microprocessor User's Manual |page=88(3-33) |accessdate=2023-12-30}}</ref>

===Release===
By 1987 it was widely known that Motorola was designing its own RISC processor. Referred to by the computer industry as the "78000",{{efn|It is not clear whether this was an official name or not.}} an homage to the earlier 68000,{{sfn|Lid}} it became the 88000 when it was released in April 1988.

As a side-effect of the complexity of the design, the CPU did not fit on a single chip. The 68030, released a year earlier, had 273,000 transistors, including the [[arithmetic logic unit]] (ALU) and [[memory management unit]] (MMU) on a single chip, with the optional [[floating point unit]] (FPU) as a separate chip. In contrast, the 88000 packaged the ALU and FPU together on the 750,000 transistor MC88100, and the [[memory management unit]] (MMU) and 16&nbsp;KB [[static RAM]] cache in the 750,000 transistor MC88200. In contrast to the 68030 where the FPU was truly optional, a practical 88000 system could not be built without at least one MC88200. Systems could include more than one MC88200, producing larger caches and allowing multiple paths to main memory for improved performance.{{sfn|Lid}}

Aimed at the high-end of the market, it was claimed to be the fastest 32-bit processor in the world when it was released. Running at 20&nbsp;MHz, it reached 34,000&nbsp;[[Dhrystones]] or 17&nbsp;[[VAX Unit of Performance|VUPS]],{{sfn|April}}{{efn|One VUPS is roughly equivalent to 1 MIPS.}} compared to about 12&nbsp;MIPS for a 12.5&nbsp;MHz [[SPARC]] of the same vintage in the [[SPARCstation]], or around 3.3&nbsp;MIPS of the 20&nbsp;MHz 68030. It was also available as a 25&nbsp;MHz part at 21&nbsp;MIPS, 48,387&nbsp;Dhrystones.{{sfn|Volume}}

At the time, Motorola marketed the 88000 strictly to the high-end of the market, including "telecommunications, artificial intelligence, graphics, three-dimensional animation, simulation, parallel processing and supercomputers", while it suggested the existing 68k series would continue to be used in the workstation market. Instead, most potential customers ignored the 88000,{{sfn|April}} and the system saw little use.

===Re-release===
As the original release saw next to no use outside Motorola's own products, and those traditional customers were starting to move to other RISC designs, the company re-launched the design in a single-chip form, the MC88110. In the late 1980s, several companies were actively examining the 88000 series for future use, including [[NeXT]], [[Apple Computer]] and [[Apollo Computer]], but all had given up on the design by the time the 88110 was finally available in 1992.

There was an attempt to popularize the system with the [[88open]] group, similar to what [[Sun Microsystems]] was attempting with its [[SPARC]] design. It appears to have failed in any practical sense.<ref name="Standards Wars">{{cite web |title=Standards Wars: Situations, Strategies and Outcomes |page=7 |url=http://www.consortiuminfo.org/bulletins/pdf/mar06/feature.pdf |publisher=ConsortiumInfo.org |date=March 2006 |author=Updegrove, Andrew |access-date=2009-06-16 |archive-date=2016-03-03 |archive-url=https://web.archive.org/web/20160303230510/http://www.consortiuminfo.org/bulletins/pdf/mar06/feature.pdf |url-status=dead }}</ref>

===Abandonment===
In the early 1990s Motorola joined the [[AIM alliance|AIM]] effort to create a new RISC architecture based on the [[IBM POWER Instruction Set Architecture|IBM POWER]] architecture. It worked a few features of the 88000 (such as a compatible bus interface<ref name="CPU of the day">{{cite web|access-date=2023-08-25|author=Cox, Steven|date=October 19, 2021|title=CPU of the Day: Motorola XC88110 88000 RISC Processor|url=https://www.cpushack.com/2013/04/02/cpu-of-the-day-motorola-xc88110-88000-risc-processor/}}</ref>) into the new [[PowerPC]] architecture to offer its customer base some sort of upgrade path. At that point the 88000 was dumped as soon as possible.<ref name="Electronic News">{{cite web|title=Motorola PowerPC deal with Ford raises questions on 88K RISC fate |url=http://findarticles.com/p/articles/mi_m0EKF/is_n1964_v39/ai_13901767/ |date=May 24, 1993 |publisher=Electronic News |author=Zipper, Stuart |access-date=2009-06-16 }}{{dead link|date=May 2017 |bot=InternetArchiveBot |fix-attempted=yes }}</ref>