Editing Motorola 68010 (section)

== Differences between 68010/68012 and 68000 ==
The 68010 and 68012 are completely user-mode compatible with the 68000, except that the MOVE from SR instruction traps in user mode, so that, to support user-mode code using that instruction, a supervisor-mode trap handler must simulate the instruction and continue the user-mode code after that instruction. This was done so that the 68010 and 68012 would meet the [[Popek and Goldberg virtualization requirements]], specifically that a new OS could run as guest and not be aware.{{r|datasheet|at=§1.3.2}} A new unprivileged MOVE from CCR instruction was added to compensate for the penalty of trapping user-mode MOVE from SR.

The 68010 and 68012 can recover from bus faults, and continue the faulting instruction, allowing them to implement [[virtual memory]]. This means that the exception stack frame is different.

A 32-bit Vector Base Register (VBR) holds the base address for the [[Exception handling|exception]] vector table. The 68000 vector table was always based at address zero.

A "loop mode" accelerates loops consisting of only a "loopable" instruction and a DBcc (Decrement/Branch on condition); an example would be MOVE and DBRA. The two-instruction mini-loop opcodes are prefetched and held in the 6-byte instruction cache while subsequent memory read/write cycles are only needed for the data operands for the duration of the loop.{{r|datasheet|at=§7.1.3}} It provided for performance improvements averaging 50%, as a result of the elimination of instruction opcodes fetching during the loop.

[[File:Motorola MC68012 0988.jpg|upright|thumb|Motorola 68012]]
[[File:Motorola MC68012 die.JPG|upright|thumb|[[Die (integrated circuit)|Die]] of Motorola 68012]]{{Anchor|Motorola 68012}}The MC68012 variant, in addition to its memory space being extended to 2&nbsp;GiB, also added a [[read-modify-write]] cycle (RMC) pin, indicating that an indivisible read-modify-write cycle in progress, in order to help the design of multiprocessor systems with virtual memory.

The expansion of the memory space in the 68012 caused an issue for any programs that used the high byte of an address to store data, a programming trick that was successful with those processors that only have a 24-bit address bus (68000 and 68010). A similar problem affected the [[68020]].