Editing Motorola 56000 (section)

== Technical description ==
[[File:Motorola DSP56001 die.JPG|thumb|180px|[[Die (integrated circuit)|Die]] of Motorola DSP56001.]]
The DSP56000 uses [[fixed-point arithmetic]], with 24-[[bit]] program [[Word (data type)|word]]s and [[24-bit]] data words. It includes two 24-bit [[processor register|registers]], which can also be referred to as a single 48-bit register. It also includes two 56-bit [[Accumulator (computing)|accumulator]]s, each  with an 8-bit "extension" ({{aka}} headroom); otherwise, the accumulators are similar to the other 24/48-bit registers. Being a [[Modified Harvard architecture]] processor, the 56k has three [[Memory space (computational resource)|memory space]]s+[[computer bus|buses]] (and on-chip memory banks in some of the models): a program memory space/bus and two data memory space/bus.<!--page_3--><ref name=fs561a/> The stack area is allocated in a separate address space, which is called "Stack Memory Space",<ref>{{cite web |url=http://cache.freescale.com/files/dsp/doc/inactive/DSP56000UM.pdf |archive-url=https://web.archive.org/web/20190119121433/http://cache.freescale.com/files/dsp/doc/inactive/DSP56000UM.pdf#page=91 |archive-date=2019-01-19 |title=DSP56000 24-BIT DIGITAL SIGNAL PROCESSOR FAMILY MANUAL |page=91(5–15) |accessdate=2023-12-26}}</ref> distinct from the main memory address space.<ref name="dsp56k-ss">{{cite web |url=http://cache.freescale.com/files/dsp/doc/inactive/DSP56000UM.pdf |archive-url=https://web.archive.org/web/20190119121433/http://cache.freescale.com/files/dsp/doc/inactive/DSP56000UM.pdf#page=29 |archive-date=2019-01-19 |title=DSP56000 24-BIT DIGITAL SIGNAL PROCESSOR FAMILY MANUAL |page=29(2–5) |accessdate=2023-12-26}}</ref> The stack, which is used when subroutine calls and "long [[interrupt]]"s, is fifteen in depth.<ref name="dsp56k-ss"/>

24 bits was selected as the basic word length because it gave the system a reasonable number range and precision for processing audio (sound), the 56000's main concern.{{citation needed|date=July 2017}} 24 bits correspond to a [[dynamic range]] of 144&nbsp;[[Decibel|dB]], sufficient in the 1980s when [[analog-to-digital converter]]s (ADCs) and [[digital-to-analog converter]]s (DACs) rarely exceeded 20 bits. One example is [[Asymmetric Digital Subscriber Line|ADSL]] applications, where filters typically require 20 bits of accuracy. The leftmost four bits are typically considered ample headroom to avoid overflow in calculations.

The processor is capable of carrying out 16.5 million instructions per second (MIPS) at the maximum specified clock speed of 33&nbsp;MHz<!--page_3-->,<ref name=fs561a/> and has hardware support for block-[[floating point]] [[Fast Fourier transform|FFT]].<!--page_3--><ref name=fs561a/> It uses 5&nbsp;V [[Transistor–transistor logic|TTL]] levels and consumes approximately 0.4&nbsp;W.<!--page_21--><ref name=fs561a/>