Editing MOS Technology 6507 (section)

== Pin configuration ==
<div class="floatright" style="border: 1px solid #828991;background-color: #f8f9fa;padding:0.2em;font-size:88%;">
{| class="wikitable" style="float:right"
|+ Pin layout of MOS 6507<ref>{{cite web|url=http://marc.info/?l=classiccmp&m=110668039327589&w=2|title=MOS 6507 Tech Spec's|author=Peter Turnbull|date=January 25, 2005}}</ref>
|-
| /RES || 1  || 28 || [[Clock signal|φ2]] out
|-
| Vss  || 2  || 27 || [[Clock signal|φ0]] in
|-
| RDY  || 3  || 26 || R/W
|-
| Vcc  || 4  || 25 || D0
|-
| A0   || 5  || 24 || D1
|-
| A1   || 6  || 23 || D2
|-
| A2   || 7  || 22 || D3
|-
| A3   || 8  || 21 || D4
|-
| A4   || 9  || 20 || D5
|-
| A5   || 10 || 19 || D6
|-
| A6   || 11 || 18 || D7
|-
| A7   || 12 || 17 || A12
|-
| A8   || 13 || 16 || A11
|-
| A9   || 14 || 15 || A10
|}
</div>
The 6507 uses a 28-pin configuration, with 13 address pins (A0..A12) and 8 data pins (D0..D7). The seven remaining pins are used for power (Vss, Vcc), the [[Clock signal|CPU timing clock]] (φ0, φ2), to reset the CPU (the /RES pin), to request a CPU wait state during its next memory read access (the RDY pin), and for the CPU to indicate if a read or write memory (or [[Memory-mapped I/O|MMIO]] device) access is being performed (the R/W pin). There is no [[Interrupt request (PC architecture)|IRQ]] or [[Non-maskable interrupt|NMI]] pin on the processor.

The RDY pin is not included on all other 28-pin cut-down versions of the 6502. Within the Atari 2600, RDY is used to synchronise the CPU to the television video lines. This function is essential for the 'racing the beam' method used by the 6502 and Atari [[Television Interface Adaptor]] chip to generate the television video signal.<ref>{{Cite web|last=Miner|first=Jay|date=October 22, 1976|title=TIA 1A – Television Interface Adaptor (Model 1A)|url=http://www.howell1964.freeserve.co.uk/Atari/tia/description.htm|url-status=live|access-date=2021-06-04|website=Internet Archive|archive-url=https://web.archive.org/web/20080424113533/http://www.howell1964.freeserve.co.uk/Atari/tia/description.htm|archive-date=2008-04-24|quote=This circuit operates on a "line by line" basis, always outputing the same information every television line unless new data is written into it by the microprocessor.}}</ref> In response to a specific address access, the TIA will assert RDY to halt the CPU until the end of the current video scan line.<ref>{{Cite web|last1=Wright|first1=Steve|last2=May|first2=Darryl|date=1988|title=2600 (STELLA) Programmer's Guide|url=https://archive.org/details/StellaProgrammersGuide/page/n5/mode/2up|access-date=2021-06-01|website=Internet Archive|quote=Simply {{sic|wri|tting|nolink=y}} to WSYNC causes the microprocessor to halt until the electron beam reaches the right edge of the screen, ...}}</ref>