Editing Interrupt latency (section)

==Background==
There is usually a trade-off between interrupt latency, [[throughput]], and processor utilization. Many of the techniques of [[microprocessor|CPU]] and [[operating system|OS]] design that improve interrupt latency will decrease throughput and increase processor utilization. Techniques that increase throughput may increase interrupt latency and increase processor utilization. Lastly, trying to reduce processor utilization may increase interrupt latency and decrease throughput.

Minimum interrupt latency is largely determined by the [[interrupt controller]] circuit and its configuration. They can also affect the [[jitter]] in the interrupt latency, which can drastically affect the [[Real-time computing|real-time]] [[Scheduling (computing)|schedulability]] of the system. The [[Intel APIC architecture]] is well known for producing a huge amount of interrupt latency jitter.{{citation needed|date=November 2015}}

Maximum interrupt latency is largely determined by the methods an OS uses for interrupt handling. For example, most processors allow programs to disable interrupts, putting off the execution of interrupt handlers, in order to protect [[critical section]]s of code. During the execution of such a critical section, all interrupt handlers that cannot execute safely within a critical section are blocked (they save the minimum amount of information required to restart the interrupt handler after all critical sections have exited).  So the interrupt latency for a blocked interrupt is extended to the end of the critical section, plus any interrupts with equal and higher priority that arrived while the block was in place.

Many computer systems require low interrupt latencies, especially [[embedded system]]s that need to [[Control system|control]] machinery in real-time.  Sometimes these systems use a [[real-time operating system]] (RTOS). An RTOS makes the promise that no more than a specified maximum amount of time will pass between executions of [[subroutine]]s. In order to do this, the RTOS must also guarantee that interrupt latency will never exceed a predefined maximum.