Editing Intel i860 (section)

==Implementations==
{{Infobox CPU
| name        = i860 XR
| image       = KL Intel i860XR.jpg
| caption     = Intel i860 XR microprocessor (33 MHz edition)
| produced-start = 1989
| produced-end = mid-1990s
| slowest     = 25  | slow-unit     = MHz
| fastest     = 40  | fast-unit     = MHz
| manuf1      = Intel
| arch        = Intel i860
| numcores = 1
| l1cache        = 4 KB (I) + 8 KB (D)
| successor      = i860 XP
}}
[[File:Intel 80860XR die.JPG|thumb|[[Die (integrated circuit)|Die]] of Intel i860 XR.]]
{{Infobox CPU
| name        = i860 XP
| image       = Intel i860 XP A80860XP-50 L4190197 top.jpg
| caption     = Intel i860 microprocessor (50 MHz edition)
| produced-start = 1991
| produced-end = mid-1990s
| slowest     = 40  | slow-unit     = MHz
| fastest     = 50  | fast-unit     = MHz
| manuf1      = Intel
| arch        = Intel i860
| transistors = 1 million<ref>Lewnes, Ann, "The Intel386 Architecture Here to Stay", Intel Corporation, Microcomputer Solutions, July/August 1989, page 2</ref>
| numcores = 1
| l1cache        = 16+16 KB
| predecessor    = i860 XR
}}
[[File:Intel 80860XP die.JPG|thumb|[[Die (integrated circuit)|Die]] of Intel i860 XP.]]

The first implementation of the i860 architecture is the i860 '''XR''' microprocessor (code-named '''N10'''), which ran at 25, 33, or 40&nbsp;MHz.  The second-generation i860 '''XP''' microprocessor (code named '''N11''') added 4 Mbyte pages, larger on-chip caches, second level cache support, faster buses, and hardware support for bus snooping to provide [[cache coherence]] in [[multiprocessor]] systems. A process shrink for the XP from 1 μm to 0.8 μm using the [[CHMOS]] V process increased the clock to 40 and 50&nbsp;MHz.<ref>{{Cite web |url=http://www.hotchips.org/wp-content/uploads/hc_archives/hc03/2_Mon/HC3.S3/HC3.3.2.pdf |title=The i860 XP - Second Generation of the i860. |access-date=2015-02-22 |archive-date=2018-08-20 |archive-url=https://web.archive.org/web/20180820124131/http://www.hotchips.org/wp-content/uploads/hc_archives/hc03/2_Mon/HC3.S3/HC3.3.2.pdf |url-status=dead }}</ref> Both microprocessors supported the same instruction set for application programs.