Editing GE-600 series (section)

==Architecture==
The 600-series CPU operates on 36-bit words,<ref name="ge-635-manual">{{cite book
|title=GE-600 Programming Reference Manual |url=http://www.bitsavers.org/pdf/ge/GE-6xx/CPB-1004_GE-635_Prog_Ref_Man_196407.pdf |publisher=[[General Electric]] |date=July 1964}}</ref>{{rp|page=II{{hyp}}17}} and addresses are 18 bits.  The ''[[Accumulator (computing)|accumulator]] Register'' (AQ) is a 72-bit register that can also be accessed separately as two 36-bit registers (A and Q) or four 18-bit registers (AU,AL,QU,QL).<ref name="ge-635-manual" />{{rp|page=II{{hyp}}5}} An eight-bit ''Exponent Register'' contain the [[Exponentiation|exponent]] for [[floating-point]] operations (the [[Significand|mantissa]] is in AQ).<ref name="ge-635-manual" />{{rp|page=II{{hyp}}5}} There are eight eighteen-bit [[index register]]s X0 through X7.<ref name="ge-635-manual" />{{rp|page=II{{hyp}}5}}

The 18-bit ''Base Address Register'' (BAR) contains the base address and number of 1024-word blocks assigned to the program.<ref name="ge-635-manual" />{{rp|page=II{{hyp}}7}}  The system also includes several special-purpose registers: an 18-bit ''Instruction Counter'' (IC) and a 24-bit ''Timer Register'' (TR) with a resolution of 15.625&nbsp;μs.<ref name="ge-635-manual" />{{rp|page=II{{hyp}}5-II{{hyp}}7}}

===Instruction formats===
The 600-series machine instructions are one word long. Operand addresses point either to operands or to ''[[indirect word]]s'', which contain the actual operand address and additional information.

Most instructions have the following format:<ref name="ge-635-manual" />{{rp|page=II{{hyp}}23}}
<pre>
                         1 1       2 2 2 2 3    3
        0                7 8       6 7 8 9 0    5
       +------------------+---------+-+-+-+------+
       |          Y       |  OP     |0|I|0| Tag  |
       +------------------+---------+-+-+-+------+
</pre>
* '''Y''' is the address field (18 bits).
* '''OP''' is the opcode (9 bits).
* '''I''' is the interrupt inhibit bit.
* '''Tag''' indicates the type of address modification to be performed.

The Repeat, Repeat Double, and Repeat Link instructions have a different format.<ref name="ge-635-manual" />{{rp|page=II{{hyp}}23}}

===Addressing modes===
The 600 series has an elaborate set of addressing modes, many of which use [[indirect word]]s, some of which are auto-incrementing or auto-decrementing.  Multiple levels of indirect addressing are supported.  Indirect addresses have the same format as instructions, and the address modification indicated by the tag field of the indirect address are performed at each level.<ref name="ge-635-manual" />{{rp|page=II{{hyp}}23}}

The tag field of the instruction consist of a 2-bit ''tag modifier'' (tm) and a 4-bit ''tag designator'' (td).<ref name="ge-635-manual" />{{rp|page=II{{hyp}}24}} The tag modifier indicates the type of modification to be performed on the instruction address:<ref name="ge-635-manual" />{{rp|page=II{{hyp}}25}}
* '''Register (R)''': Add the address field (Y) to the contents of the register indicated by the tag designator. 
* '''Register then indirect (RI)''': Perform the address modification as in Register modification, use the word at the effective address as an indirect address of the operand.
* '''Indirect then register (IR)''': Obtain the indirect word from the address specified by Y, and perform the modification requested by the tag field of the indirect word. This may result in multiple levels of indirection.  Perform the address modification specified by the instruction on the last indirect word encountered.
* '''Indirect then tally (IT)''': Obtain the indirect word from the address specified by Y, then use the address in the indirect word as the effective address. Bits 30-35 of the indirect word contained a ''tally'' field which could be used for addressing characters within a word.

For modification types R, RI, and IR the tag designator contains a register to be used for indexing (X0-X7,AU,AL,QU,QL,IC). Other TD values indicate that Y should be used as an immediate operand.  Direct addressing is a special case where Y is used as the operand address with no modification.<ref name="ge-635-manual" />{{rp|page=II{{hyp}}26}}

For modification type IT, the indirect word contains an 18-bit address, a 12-bit tally, and a 6-bit tag. The tag designator indicates the operation to be performed, some of which increment the address and decrement the tally of the indirect word or decrement the address and increment the tally of the indirect word. The '''Character from Indirect''' and '''Sequence Character'''  operations can be used to address 6-bit and 9-bit [[byte]]s; this supports extracting specific bytes, and incrementing the byte pointer, but not random access to bytes.<ref name="ge-635-manual" />{{rp|page=II{{hyp}}26-II{{hyp}}33a}}<ref>cf. [[Byte addressing#Hybrid systems]]</ref>

===Data formats===
Data was stored in [[Big-endian#Big-endian|big-endian format]].  Bits were numbered starting from 0 (most-significant) to 35 or 71 (least-significant).<ref name=Guide>{{cite book|last=Honeywell, Inc.|title=GMAP Pocket Guide|date=July 1974|url=http://www.bitsavers.org/pdf/honeywell/large_systems/GCOS/BS16_GMAP_Pocket_Guide_Jul74.pdf}}</ref>

*'''Binary fixed-point data''' was stored in [[twos-complement]].  Half-word (18-bits), word (36-bits) and double-word (72-bits) operands were supported. Multiply and divide instructions were provided which would treat the operand as a binary fraction rather than an integer.
*'''Binary floating-point data''' could be single precision (36 bits) or double precision (72 bits).  In either case the exponent was eight bits, twos-complement binary.  The mantissa was either 28 or 64 bits, twos-complement binary. Operands and results in the AQ and E registers have up to 72 bis of mantissa.
*'''Character data''' was either 6-bit BCD or 9-bit ASCII.

===I/O===
The 600-series also included a number of [[channel controller]]s for handling [[Input/output|I/O]]. The [[Central processing unit|CPU]] could hand off short programs written in the channel controller's own [[machine language]], which would then process the data, move it to or from the memory, and raise an [[interrupt]] when they completed. This allowed the main CPU to move on to other tasks while waiting for the slow I/O to complete, a primary feature of [[time sharing]] systems.